View EM78468Q_1237073.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

EM78468
8-BIT Microcontroller
Product Specification
DOC. VERSION 1.1
ELAN MICROELECTRONICS CORP.
April 2005
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.
Copyright (c) 2005 by ELAN Microelectronics Corporation Printed in Taiwan
All Rights Reserved
The contents of in this specification are subject to change without notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible to any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising out of the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESS WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Science-based Industrial Park Hsinchu, Taiwan, 308 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8223 Fax: +1 408 366-8220
Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com
Shanghai: Elan Microelectronics Shanghai Corporation, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 021 5080-3866 Fax: +86 021 5080-4600
Contents
Contents
1 GENERAL DESCRIPTION ******************************************************************************************** 1 2 FEATURES********************************************************************************************************************* 1
2.1 2.2 2.3 CPU*********************************************************************************************************************************************** 1 LCD Circuit ************************************************************************************************************************************ 2 Applications *********************************************************************************************************************************** 2
3 PIN ASSIGNMENTS ****************************************************************************************************** 3
3.1 3.2 3.3 3.4 QFP - 64**************************************************************************************************************************************** 3 LQFP - 64************************************************************************************************************************************** 4 LQFP - 44************************************************************************************************************************************** 5 QFP - 44**************************************************************************************************************************************** 6
4 FUNCTION DESCRIPTION ******************************************************************************************* 9
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 Operational Registers****************************************************************************************************************** 10 Special Purpose Registers*********************************************************************************************************** 19 TCC and WDT Pre-scaler************************************************************************************************************ 27 I/O Ports ************************************************************************************************************************************** 30 RESET and Wake-up ****************************************************************************************************************** 31 Oscillator ************************************************************************************************************************************* 36 Power-on Considerations ************************************************************************************************************ 38 Interrupt *************************************************************************************************************************************** 40 LCD Driver*********************************************************************************************************************************** 42 Infrared Remote Control Application / PWM Waveform Generate************************************************ 48 Code Options ****************************************************************************************************************************** 52 Instruction Set ***************************************************************************************************************************** 53 Timing Diagram *************************************************************************************************************************** 55
5 ABSOLUTE MAXIMUM RATINGS ****************************************************************************** 56 6 ELECTRICAL CHARACTERISTIC****************************************************************************** 57
6.1 6.2 DC ELECTRICAL CHARACTERISTICS************************************************************************************** 57 AC Electrical Characteristics ******************************************************************************************************* 59
7 Application Circuit****************************************************************************************************** 60 APPENDIX A
A.1 A.2 Package Types **************************************************************************************************************************** 61 Package Information******************************************************************************************************************** 61
APPENDIX B
B.1 B.2 ICE 468XA Oscillator circuit (JP 5) ********************************************************************************************** 65 ICE 468XA output pin assignment (JP 3)************************************************************************************* 67
* iii
Product Specification (V1.1) 04.11.2005
Contents
Specification Revision History
Version Revision Description Date
1.0 1.1
Initial version Add LQFP 64 package
2005//03/02 2005/04/11
iv *
Product Specification (V1.1) 04.11.2005
EM78468
8-BIT Microcontroller
1
GENERAL DESCRIPTION
This LSI is an 8-bit RISC type microprocessor with high speed CMOS technology and low power consumption. Integrated onto a single chip are on chip watchdog timer (WDT), Data RAM, ROM, programmable real time clock counter, internal/external interrupt, power down mode, LCD driver, infrared transmitter function, and tri-state I/O. The EM78468 provides a seven option bits to accommodate user's requirements.
2
FEATURES
2.1 CPU
Operating voltage and temperature range: 2.2V ~ 5.5 V. (at 0~+70) Operation speed: DC ~ 10MHz clock input. Dual clock operation High frequency oscillator can select among Crystal, RC, or PLL (phase lock loop) Low frequency oscillator can select between Crystal or RC mode Totally 272 bytes SRAM 144 bytes general purpose register 128 bytes on chip data RAM 4K*13 bits MASK - ROM Up to 28 bi-directional tri-state I/O ports Typically, 12 bi-directional tri-state I/O ports. 16 bi-directional tri-state I/O ports shared with LCD segment output pin. 8-level stack for subroutine nesting 8-bit real time clock/counter (TCC) One infrared transmitter/PWM generator function Four sets of 8 bits auto reload timer can be used as interrupt sources Counter 1: independent down-count timer. Counter 2, High Pulse Width Timer (HPWT), and Low Pulse Width Timer (LPWT) shared with IR function. Programmable free running on chip watchdog timer (WDT). This function can operate on Normal, Green and Idle mode.
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
*1
EM78468
8-BIT Microcontroller Operation modes: Normal mode: The CPU operated on frequency of main oscillator (Fm) Green mode: The CPU operated on frequency sub-oscillator (Fs) and main oscillator (Fm) stop. Idle mode: CPU idle, LCD display remains working Sleep mode: whole chip stop working. Input port wake up function (PORT6, PORT8). Working on Idle and sleep mode. Eight interrupt sources, three external and five internal. Internal interrupt source : TCC; Counter 1,2; High/Low pulse width timer. External interrupt source : INT0, INT1 and Pin change wake-up (Port 6 and Port 8) Packages: Dice form : 59 pin QFP-64 pin : EM78468Q (Body 14mm*20mm) LQFP-64 pin : EM78468AQ (Body 7mm*7mm) LQFP-44 pin : EM78468BQ (Body 10mm*10mm) QFP-44 pin : EM78468CQ (Body 10mm*10mm)
2.2 LCD Circuit
Common driver pins: 4 Segment driver pins: 32 LCD Bias: 1/3, 1/2 bias LCD Duty: 1/4, 1/3, 1/2 duty
2.3 Applications
Remote control for air conditioner Health care Home appliances
2*
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
3
PIN ASSIGNMENTS
3.1 QFP - 64
SEG29/P8.5 SEG30/P8.6 SEG31/P8.7 P5.7/IROUT P5.5/INT1 3 3 32 31 30 29 P5.4/INT0 XOUT XIN VDD OSCO R-OSCI GND /RESET VLCD3 VLCD2 VA VB COM0 28 27 26 25 24 23 22 21 20 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 COM1 P5.6/TCC 3 4 COM2 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 NC NC NC P6.7 P6.0 NC 3 6 SEG 0 NC 3 5 COM3
5 1 SEG28/P8.4 SEG27/P8.3 SEG26/P8.2 SEG25/P8.1 SEG24/P8.0 SEG23/P7.7 SEG22/P7.6 SEG21/P7.5 SEG20/P7.4 SEG19/P7.3 SEG18/P7.2 SEG17/P7.1 SEG16/P7.0 52 53 54 55 56 57 58 59 60 61 62 63 64
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
EM78468Q QFP-64
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG 4
SEG 3
SEG 2
SEG 9
SEG 8
SEG 7
SEG 6
Input Pin Output Pin Input/Output Pin Digital I/O Pin/LCD Output Pin LCD Output Pin
Fig. 1-(a) Pins Configuration for 64 Pin QFP Package
SEG 5
SEG 1
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
*3
EM78468
8-BIT Microcontroller
3.2 LQFP - 64
SEG31/P8.7 P5.7/IROUT P5.5/INT1 3 3 32 31 30 29 28 27 P5.4/INT0 XOUT XIN VDD OSCO R-OSCI GND /RESET VLCD3 VLCD2 VA VB COM0 COM1 COM2 COM3 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 SEG 0 P5.6/TCC 3 4 SEG 1 P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 NC NC P6.0 NC 3 6 SEG 3 NC 3 5 SEG 2
4 8 NC SEG28/P8.6 SEG28/P8.5 SEG28/P8.4 SEG27/P8.3 SEG26/P8.2 SEG25/P8.1 SEG24/P8.0 SEG23/P7.7 SEG22/P7.6 SEG21/P7.5 SEG20/P7.4 SEG19/P7.3 SEG18/P7.2 SEG17/P7.1 SEG16/P7.0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
EM78468AQ LQFP-64
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG 9
SEG 8
SEG 7
SEG 6
Input Pin Output Pin Input/Output Pin Digital I/O Pin/LCD Output Pin LCD Output Pin
Fig. 1-(b) Pins Configuration for 64 Pin LQFP Package
4*
SEG 5
(This specification is subject to change without further notice)
SEG 4
Product Specification (V1.1) 04.11.2005
EM78468
8-BIT Microcontroller
3.3 LQFP - 44
SEG28/P8.4 P5.7/IROUT 2 4 P5.6/TCC 2 3 22 21 20 P5.5/INT1 P5.4/INT0 XOUT XIN VDD OSCO R-OSCI GND /RESET VLCD3 VLCD2 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 1 0 1 1 VA P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 2 6 COM1 P6.7 P6.0 2 5 COM0
3 3 SEG27/P8.3 SEG26/P8.2 SEG25/P8.1 SEG24/P8.0 SEG23/P7.7 SEG22/P7.6 SEG21/P7.5 SEG20/P7.4 SEG19/P7.3 SEG18/P7.2 SEG17/P7.1 34 35 36 37 38 39 40 41 42 43 44
3 2
3 1
3 0
2 9
2 8
2 7
EM78468BQ LQFP-44
SEG16/P7.0
SEG14
SEG13
SEG12
SEG11
COM3
COM2
Input Pin Output Pin Input/Output Pin Digital I/O Pin/LCD Output Pin LCD Output Pin
Fig. 1-(c) Pins Configuration for 44 Pin LQFP Package
VB
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
*5
EM78468
8-BIT Microcontroller
3.4 QFP - 44
SEG28/P8.4 P5.7/IROUT 2 4 P5.6/TCC 2 3 22 21 20 P5.5/INT1 P5.4/INT0 XOUT XIN VDD OSCO R-OSCI GND /RESET VLCD3 VLCD2 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 1 0 1 1 VA P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 2 6 COM1 P6.7 P6.0 2 5 COM0
3 3 SEG27/P8.3 SEG26/P8.2 SEG25/P8.1 SEG24/P8.0 SEG23/P7.7 SEG22/P7.6 SEG21/P7.5 SEG20/P7.4 SEG19/P7.3 SEG18/P7.2 SEG17/P7.1 34 35 36 37 38 39 40 41 42 43 44
3 2
3 1
3 0
2 9
2 8
2 7
EM78468CQ QFP-44
SEG16/P7.0
SEG14
SEG13
SEG12
SEG11
COM3
COM2
Input Pin Output Pin Input/Output Pin Digital I/O Pin/LCD Output Pin LCD Output Pin
Fig. 1-(d) Pins Configuration for 44 Pin QFP Package
6*
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
VB
EM78468
8-BIT Microcontroller Table 1 (a) Pin Description for Package of QFP64 and LQFP64
Pin Pin Number I/O type Description
VDD GND
29 26
I I
R-OSCI
27
I
OSCO Xin Xout /RESET
28 30 31 25
O I O I
P5.4/INT0
32
I/O
P5.5/INT1
33
I/O
* Power supply pin * System ground pin * In crystal mode: crystal input * In RC mode: resistor pull high. * In PLL mode: connect 0.01F capacitance to GND * Connect 0.01F capacitor to GND and code option select PLL mode when high oscillator is not use. * In crystal mode: crystal output * In RC mode: instruction clock output * In crystal mode: Input pin for sub-oscillator. Connect to a 32.768KHz crystal * RC mode: this pin is connected with a resistor to high level. * In crystal: Connect to a 32.768KHz crystal * In RC mode: instruction clock output * Low active. If set as /RESET and remains at logic low, the devices will be reset * General purpose I/O pin. /external interrupt. * INT0 interruption source can be set to falling or rising edge by IOC71 register bit 7 (INT_EDGE). * Wake up from sleep mode and idle mode when the pin status changes. * General purpose I/O pin. /external interrupt. * Interruption source is a falling edge signal. * Wake up from sleep mode and idle mode when the pin status changes. * General purpose I/O/ external counter input * This pin works in normal/green/idle mode. * General purpose I/O pin or IR/PWM mode output pin, * Capable of sinking 18mA/5V. * General purpose I/O pin. * Pull-high, pull-low and open drain function support. * All pins can wake up from sleep and idle modes when the pin status changes. * LCD common output pin. * LCD segment output pin. * LCD segment output pin. Can be shared with general purposes I/O pin * LCD segment output pin. Can be shared with general I/O pin * For general purpose I/O use, can wake up from sleep mode and idle mode when the pin status changes. * For general purposes I/O use, supports pull-high function. * Connect capacitors for LCD bias voltage * Connect capacitors for LCD bias voltage * One of LCD bias voltage * One of LCD bias voltage
P5.6/TCC P5.7/IROUT P6.0 ~ P6.7 COM3~0 SEG0~SEG15 SEG16/P7.0 ~ SEG23/P7.7 SEG24/P8.0 ~ SEG30/P8.6 SEG31/P8.7 VB VA VLCD2 VLCD3 NC
34 37
I/O I/O
38~45
I/O O O O/(I/O)
17~20 16~1 64
~
57 56 ~ 50 46 21 22 23 24 35~36 47~49
O/(I/O)
O O O O
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
*7
EM78468
8-BIT Microcontroller Table 1 (b) Pin Description for Package of QFP44 and LQFP44 Pin VDD GND Pin Number 18 15 I/O type I I Description * Power supply pin * System ground pin * In crystal mode: crystal input * In RC mode: resistor pull high. * In PLL mode: connect 0.01F capacitance to GND * Connect 0.01F capacitance to GND and code option select PLL mode when high oscillator is not use. * In crystal mode: crystal output * In RC mode: instruction clock output * In crystal mode: Input pin for sub-oscillator. Connect to a 32.768KHz crystal * RC mode: this pin is connected with a resistor to high level. * In crystal: Connect to a 32.768KHz crystal * In RC mode: instruction clock output * Low active. If set as /RESET and remains at logic low, the devices will be reset * General purpose I/O pin. /external interrupt. * INT0 interruption source can be set to falling or rising edge by IOC71 register bit 7 (INT_EDGE). * Wake up from sleep mode and idle mode when the pin status changes. * General purpose I/O pin. /external interrupt. * Interruption source is a falling edge signal. * Wake up from sleep mode and idle mode when the pin status changes. * General purpose I/O/ external counter input * This pin works in normal/green/idle mode. * General purpose I/O pin or IR/PWM mode output pin, * Capable of sinking 18mA/5V. * General purpose I/O pin. * Pull-high, pull-low and open drain function support. * All pins can wake up from sleep and idle modes when the pin status changes. * LCD common output pin. * LCD segment output pin. * LCD segment output pin. Can be shared with general purposes I/O pin * LCD segment output pin. Can be shared with general I/O pin * For general purpose I/O use, can wake up from sleep mode and idle mode when the pin status changes. * For general purposes I/O use, supports pull-high function. * Connect capacitors for LCD bias voltage * Connect capacitors for LCD bias voltage * One of LCD bias voltage * One of LCD bias voltage
R-OSCI
16
I
OSCO Xin Xout /RESET
17 19 20 14
O I O
I
P5.4/INT0
21
I/O
P5.5/INT1
22
I/O
P5.6/TCC P5.7/IROUT P6.0 ~ P6.7 COM3~0 SEG11~SEG14 SEG16/P7.0 SEG17/P7.1 ~ SEG23/P7.7 SEG24/P8.0 ~ SEG31/P8.4 VB VA VLCD2 VLCD3
23 24
I/O I/O
25~32 6~9 5~2 1 44 ~ 38 37 ~ 33 10 11 12 13
I/O O O O/(I/O)
O/(I/O) O O O O
8*
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
4
FUNCTION DESCRIPTION
CPU Data RAM
Timing Control
LCD driver
LCD
ROM
IO PORT
I/O
Oscillator PLL/Crystal/RC
IR/PWM
Timer/ Counter
R-OSCI
OSCO
Xout
Xin
Oscillator Timing Control
WDT timer
ROM
R2
STACK
R1 (TCC) Interruption control
Interruption register
Control w ake-up on I/ O port
General RAM
Instruction decoder R3
ALU
R4
ACC
Data & Control BUS
128 byte Data RAM
LCD RAM
PORT5 IOC5 R 5
PORT6 IOC6 R 6
PORT7 IOC9 R 7
PORT8 IOC9 R 8
Common driver
Segment driver
Fig. 2 System Block Diagram
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
*9
EM78468
8-BIT Microcontroller
4.1 Operational Registers
4.1.1 R0/IAR (Indirect Addressing Register) (Address: 00h)
R0 is not a physically implemented register. It is used as indirect addressing pointer. Any instruction using R0 as register actually accesses the data pointed by the RAM Select Register (R4).
4.1.2
R1/TCC (Time Clock /Counter) (Address: 01h)
Increases by an external signal edge applied to TCC, or by the instruction cycle clock. Written and read by the program as any other register.
4.1.3
R2/PC (Program Counter) (Address: 02h)
* The structure is depicted in Fig. 3 * Generates 4K x 13 on-chip ROM addresses to the relative programming instruction codes. * "JMP" instruction allows direct loading of the low 10 program counter bits. * "CALL" instruction loads the low 10 bits of the PC and PC+1, then push it into the stack. * "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. * "MOV R2, A" allows the loading of an address from the A register to the PC. The contents of the ninth and tenth bits do not change. * "ADD R2, A" allows a relative address be added to the current PC. * The most significant bit (A10~A11) will be loaded with the content of bits PS0~PS1 in the Status register (R3) upon execution of a "JMP'' or "CALL'' instruction.
10 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
R3
PC
00 PAGE0 0000~03FF 01 PAGE1 0400~07FF 10 PAGE2 0800~0BFF 11 PAGE3 0C00~0FFF
A11
A10
A9 A8
A7
~
A0
Reset v ector TCC ov erf low interrupt v ector Exteral INT0 pin interrupt v ector Exteral INT1 pin interrupt v ector Counter 1 underf low interrupt v ector Counter 2 underf low interrupt v ector high pulse width timer underf low interrupt v ector low pulse width timer underf low interrupt v ector Port 6,Port8 pin change wake-up interrupt v ector
000H 003H 006H 009H 00CH 00FH 012H 015H 018H
CALL RET RETL RETI
STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 STACK LEVEL 7 STACK LEVEL 8
User Memory Space
On-Chip Programmemory
FFFH
Fig. 3 Program Counter Organization
ADDRESS 0 0 IAR (Indirect Addressing Register) 0 1 TCC (Time Clock Counter) 0 2 PC (Program Counter) 0 3 SR (Status Register) 0 4 RSR (RAM select register) 0 5 PORT5 (Port 5 & IOCPAGE Control) 0 6 PORT6 (Port6 I/O data register) 0 7 PORT7 (Port7 I/O data register) 0 8 PORT8 (Port8 I/O data register) 0 9 LCDCR (LCD control register) 0 A LCD_ADDR (LCD address) 0 B LCD_DB (LCD data buffer) 0 C CNTER (Counter enable register) 0 D SBPCR (System, Booster , PLL control) 0 E IRCR (IR, Pin of IR;INT0/1;TCC control) 0 F ISR (interrupt status register) 10 | 1F 20 | 3F
R5 bit 0 -> 0 control register page 0
R5 bit 0 -> 1 control register page 1
P5CR (Port5 I/O & LCD segment control) P6CR (Port6 I/O control register) P7CR (Port7 I/O control register) P8CR (Port8 I/O control register) RAM_ADDR (128 byte RAM address) RAM_DB (128 byte RAM data buffer) CNT1PR (Counter 1 preset register) CNT2PR (Counter 2 preset register) HPWTPR (High-pulse width timer preset) LPWTPR (Low-pulse width timer preset) IMR (interrupt mask register) WUCR (Wake up & P5.7 sink current) TCCCR (TCC & INT0 control register) WDTCR (WDT control register) CNT12CR (Counter 1,2 control register) HLPWTCR (high/low pulse width timer control) P6PH (Port 6 pull-high control register) P6OD (Port 6 open drain control register) P8PH (Port 8 pull-high control register) P6PL (Port 6 pull-low control register)
16 byte common register
LCD RAM 4*32 bits
bank 0 ~ bank 3 32 byte common register
128 byte data RAM
Fig. 4 Data Memory Configuration
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 11
EM78468
8-BIT Microcontroller
4.1.4 R3/SR (Status Register) (Address: 03h)
Bit 7 -Bit 6 PS1 Bit 5 PS0 Bit 4 T Bit 3 P Bit 2 Z Bit 1 DC Bit 0 C
Bit 7: Not used Bit 6, 5 (PS1 ~ PS0): Page select bits PS1 PS0 ROM Page (Address) 0 0 1 1 0 1 0 1 Page 0 (000H ~ 3FFH) Page 1 (400H ~ 7FFH) Page 2 (800H ~ BFFH) Page 3 (C00H ~ FFFH)
PS0~PS1 are used to select a ROM page. User can use PAGE instruction (e.g. PAGE 1) or set PS1~PS0 bits to change ROM page. When executing a "JMP", "CALL", or other instructions which causes the program counter to be changed (e.g. MOV R2, A), PS0~PS1 are loaded into the 11th and 12th bits of the program counter where it selects one of the available program memory pages. Note that RET (RETL, RETI) instruction does not change the PS0~PS1 bits. That is, the return will always be to the page from where the subroutine was called, regardless of the current setting of PS0~PS1 bits. Bit 4 (T): Time-out bit. Set to 1 by the "SLEP" and "WDTC" commands or during power up and reset to 0 by WDT timeout. EVENT T P REMARK WDT wake up from sleep mode WDT time out (not sleep mode) /RESET wake up from sleep Power up Low pulse on /RESET 0 0 1 1 1 0 1 0 1 1 X: don't care
Bit 3 (P): Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 2 (Z): Zero flag Bit 1 (DC): Auxiliary carry flag. Bit 0 (C): Carry flag
4.1.5
R4/RSR (RAM Select Register) (Address: 04h)
Bit 7 RBS1 Bit 6 RBS0 Bit 5 RSR5 Bit 4 RSR4 Bit 3 RSR3 Bit 2 RSR2 Bit 1 RSR1 Bit 0 RSR0
Bits 7 ~ 6 (RBS1 ~ RBS0) determine which bank is activated among the 4 banks. See the configuration of the data memory in Fig.4. Use BANK instruction (e.g. BABK 1) to change bank.
12 * Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller Bits 5 ~ 0 (RSR 5 ~ RSR 0) are used to select up to 64 registers (address: 00~3F) in the indirect addressing mode. If no indirect addressing is used, the RSR can be used as an 8-bit general purposes read/writer register.
4.1.6
R5/PORT5 (PORT 5 I/O Data and Page of Register Select) (Address: 05h)
Bit 7 R57 Bit 6 R56 Bit 5 R55 Bit 4 R54 Bit 3 -Bit 2 -Bit 1 -Bit 0 IOCPAGE
Bit 7~4: 4-bits I/O registers of PORT5 User can use IOC50 register to define input or output each bit. Bit 3~1: Not used Bit 0 (IOCPAGE): change IOC5 ~ IOCF to another page, 0/1 => page0 / page1 IOCPAGE = "0": Page 0 (select register of IOC50 to IOCF0) IOCPAGE = "1": Page 1 (select register of IOC61 to IOCE1)
4.1.7 R6/PORT6 (PORT 6 I/O Data Register) (Address: 06h)
Bit 7 R67 Bit 6 R66 Bit 5 R65 Bit 4 R64 Bit 3 R63 Bit 2 R62 Bit 1 R61 Bit 0 R60
Bit 7~0: 8-bit I/O registers of PORT 6 User can use IOC60 register to define input or output each bit.
4.1.8
R7/PORT7 (PORT 7 I/O Data Register) (Address: 07h)
Bit 7 R77 Bit 6 R76 Bit 5 R75 Bit 4 R74 Bit 3 R73 Bit 2 R72 Bit 1 R71 Bit 0 R70
Bit 7~0: 8-bit I/O registers of PORT 7 User can use IOC70 register to define input or output each bit.
4.1.9
R8/PORT8 (PORT 8 I/O Data Register) (Address: 08h)
Bit 7 R87 Bit 6 R86 Bit 5 R85 Bit 4 R84 Bit 3 R83 Bit 2 R82 Bit 1 R81 Bit 0 R80
Bit 7~0: 8-bit I/O registers of PORT 8 User can use IOC80 register to define input or output each bit.
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 13
EM78468
8-BIT Microcontroller
4.1.10 R9/LCDCR (LCD Control Register) (Address: 09h)
Bit 7 BS Bit 6 DS1 Bit 5 DS0 Bit 4 LCDEN Bit 3 -Bit 2 LCDTYPE Bit 1 LCDF1 Bit 0 LCDF0
Bit 7 (BS): LCD bias select bit, BS = "0": 1/2 bias BS = "1": 1/3 bias Bit 6 ~ 5 (DS1 ~ DS0): LCD duty select DS1 DS0 LCD duty 0 0 1 0 1 X 1/2 duty 1/3 duty 1/4 duty
Bit 4 (LCDEN): LCD enable bit. LCDEN = " 0": LCD circuit disable, all common/segment outputs are set to ground (GND) level. LCDEN = "1": LCD circuit enable Bit 3: Not used Bit 2 (LCDTYPE): LCD drive waveform type select bit LCDTYPE = "0": A type waveform LCDTYPE = "1": B type waveform Bit 1 ~ 0 (LCDF1 ~ LCDF0): LCD frame frequency control bits LCD frame frequency (e.g. Fs=32.768KHz) LCDF1 LCDF0 1/2 duty 1/3 duty 1/4 duty 0 0 1 1 0 1 0 1 Fs/(256*2)=64.0 Fs/(280*2)=58.5 Fs/(304*2)=53.9 Fs/(232*2)=70.6 Fs/(172*3)=63.5 Fs/(188*3)=58.0 Fs/(204*3)=53.5 Fs/(156*3)=70.0 Fs/(128*4) =64.0 Fs/(140*4) =58.5 Fs/(152*4) =53.9 Fs/(116*4) =70.6
Fs: sub-oscillator frequency
4.1.11 RA/LCD_ADDR (LCD Address) (Address: 0Ah)
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 LCD_A4 Bit 3 LCD_A3 Bit 2 LCD_A2 Bit 1 LCD_A1 Bit 0 LCD_A0
Bit 7 ~ 5: Not used, fixed to "0"
14 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller Bit 4 ~ 0 (LCDA4 ~ LCDA0): LCD RAM address RA (LCD address) Bit 7 ~4 00H 01H 02H | 1DH 1EH 1FH Common ---X COM3 COM2 COM1 COM0 ---|
RB (LCD data buffer)
Bit 3 Bit 2 Bit 1 Bit 0 (LCD_D3) (LCD_D2) (LCD_D1) (LCD_D0)
Segment
SEG0 SEG1 SEG2 | SEG29 SEG30 SEG31
4.1.12 RB/LCD_DB (LCD Data Buffer) (Address: 0Bh)
Bit 7 -Bit 6 -Bit 5 -Bit 4 -Bit 3 Bit 2 Bit 1 Bit 0 LCD_D 3 LCD_D 2 LCD_D 1 LCD_D 0
Bit 7 ~ 4: Not used Bit 3~0 (LCD_D3 ~ LCD_D0): LCD RAM data transfer register
4.1.13 RC/CNTER (Counter Enable Register) (Address: 0Ch)
Bit 7 -Bit 6 -Bit 5 -Bit 4 -Bit 3 Bit 2 Bit 1 Bit 0 LPWTEN HPWTEN CNT2EN CNT1EN
Bit 7,5: Not used, must fixed to "0" Bit 6,4: Not used Bit 3(LPWTEN): low pulse width timer enable bit, LPWTEN = "0": Disable LPWT. Count operation stop. LPWTEN = "1": Enable LPWT. Count operation start. Bit 2(HPWTEN): high pulse width timer enable bit HPWTEN = "0": Disable HPWT. Count operation stop. HPWTEN = "1": Enable HPWT. Count operation start. Bit 1(CNT2EN): counter 2 enable bit CNT2EN = "0": Disable Counter 2. Count operation stop. CNT2EN = "1": Enable Counter 2. Count operation start. Bit 0(CNT1EN): counter 1 enable bit CNT1EN = "0": Disable Counter 1. Count operation stop.
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 15
EM78468
8-BIT Microcontroller CNT1EN = "1": Enable Counter 1. Count operation start.
4.1.14 RD/SBPCR (System, Booster and PLL Control Register) (Address: 0Dh)
Bit 7 -Bit 6 CLK2 Bit 5 CLK1 Bit 4 CLK0 Bit 3 IDLE Bit 2 BF1 Bit 1 BF0 Bit 0 CPUS
Bit 7: Not used Bit 6 ~ 4 (CLK2 ~ CLK0): main clock selection bits for PLL mode (code option select) CLK2 CLK1 CLK0 Main clock Example Fs=32.768K 0 0 0 0 1 0 0 1 1 X 0 1 0 1 X Fs*130 Fs*65 Fs*65/2 Fs*65/4 Fs*244 4.26 MHz 2.13 MHz 1.065 MHz 532 KHz 8 MHz
Bit 3 (IDLE): idle mode enable bit. This bit will decide the intended mode of the SLEP instruction. IDLE="0"+SLEP instruction => sleep mode IDLE="1"+SLEP instruction => idle mode * NOP instruction must be added after SLEP instruction. Example: IDLE mode: IDLE bit = "1" +SLEP instruction + NOP instruction SLEEP mode: IDLE bit = "0" +SLEP instruction + NOP instruction Bit 2 ~ 1 (BF1 ~ BF0): LCD booster frequency select bit to adjust VLCD 2,3 driving. BF1 BF0 Booster frequency 0 0 1 1 0 1 0 1 Fs Fs/4 Fs/8 Fs/16
Bit 0 (CPUS): CPU oscillator source select, When CPUS=0, the CPU oscillator select sub-oscillator and the main oscillator is stopped. CPUS = "0": sub-oscillator (Fs) CPUS = "1": main oscillator (Fm)
16 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
CPU Operation Mode
Code option HLFS=1
RESET
Code option HLFS=0
Normal Mode fm:oscillation fs:oscillation
it must delay a little times for the main oscillation stable w hile your system timing control is conscientious
CPU: using fosc CPUS="0"
CPUS="1" SLEEP Mode Fm:stop Fs: stop CPU: stop
Wake up IDLE="0" SLEP
Green Mode fm:stop fs:oscillation CPU: using fs
IDLE="1" SLEP
IDLE Mode fm:stop fs:oscillation
w ake up
CPU: stop
The w ake up time from sleep to green mode is approximately sub-oscillator setup time +18ms+16*1/fs
The w ake up time from idle to green mode is 16*1/fs
Fig. 5 CPU Operation Mode
4.1.15 RE/IRCR (IR and PORT 5 Setting Control Register) (Address: 0Eh)
Bit 7 IRE Bit 6 HF Bit 5 LGP Bit 4 -Bit 3 IROUTE Bit 2 TCCE Bit 1 EINT1 Bit 0 EINT0
Bit 7 (IRE): Infrared Remote Enable bit IRE = "0": Disable IR/PWM function. The state of P5.7/IROUT pin is determined by bit 7 of IOC50 if it's for IROUT. IRE = "1": Enable IR or PWM function. Bit 6 (HF): High carry frequency. HF = "0": For PWM application, disable H/W modulator function. IROUT waveform is created according to high-pulse and low-pulse time as determined by the high pulse and low pulse width timers respectively. The counter 2 is an independent auto reload timer. HF = "1": For IR application mode, enable H/W modulator function, the low time sections of the generated pulse is modulated with the frequency Fcarrier. The frequency of Fcarrier provide by counter 2. Bit 5 (LGP): IROUT for long time of low pulse. LGP = "0": The high-pulse width timer register and low-pulse width timer is valid. LGP = "1": The high-pulse width timer register is ignored. So the IROUT waveform is dependent on low-pulse width timer register only. Bit 4: Not used
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 17
EM78468
8-BIT Microcontroller Bit 3 (IROUTE): Define the function of P5.7/IROUT pin. IROUTE = "0": for bi-directional general I/O pin. IROUTE = "1": for IR or PWM output pin, the control bit of P5.7 (bit 7 of IOC50) must be set to "0" Bit 2 (TCCE): Define the function of P5.6/TCC pin. TCCE = "0": for bi-directional general I/O pin. TCCE = "1": for external input pin of TCC, the control bit of P5.6 (bit 6 of IOC50) must be set to "1" Bit 1 (EINT1): Define the function of P5.5/INT1 pin. EINT1 = "0": for bi-directional general I/O pin. EINT1 = "1": for external interrupt pin of INT1, the control bit of P5.5 (bit 5 of IOC50) must be set to "1" Bit 0 (EINT0): Define the function of P5.4/INT0 pin. EINT0 = "0": for bi-directional general I/O pin. EINT0 = "1": for external interrupt pin of INT0, the control bit of P5.4 (bit 4 of IOC50) must be set to "1"
4.1.16 Address: 0Fh; RF/ISR (Interrupt Status Register)
Bit 7 ICIF Bit 6 LPWTF Bit 5 HPWTF Bit 4 CNT2F Bit 3 CNT1F Bit 2 INT1F Bit 1 INT0F Bit 0 TCIF
These bits are set to "1" when interrupt occurs respectively. Bit 7 (ICIF): PORT 6, PORT 8, input status changed interrupt flag. Set when PORT6, PORT8 input changes. Bit 6 (LPWTF): interrupt flag of internal low-pulse width timer underflow. Bit 5 (HPWTF): interrupt flag of internal high-pulse width timer underflow. Bit 4 (CNT2F): interrupt flag of internal counter 2 under-flow. Bit 3 (CNT1F): interrupt flag of internal counter 1 underflow. Bit 2 (INT1F): external INT1 pin interrupt flag. Bit 1 (INT0F): external INT0 pin interrupt flag. Bit 0 (TCIF): TCC timer overflow interrupt flag. Set when TCC timer overflows.
4.1.17 Address: 10h~3Fh;R10~R3F (General Purpose Register)
R10~R31F and R20~R3F (Banks 0~3) are general purposes register.
18 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
4.2 Special Purpose Registers
4.2.1 A (Accumulator)
Internal data transfer, or instruction operand holding This is not an addressable register.
Registers of IOC Page 0 (IOC50 ~ IOCF0, Bit 0 of R5 = "0") 4.2.2 IOC50/P5CR (PORT 5 I/O and PORT 7, 8 for LCD Segment Control Register) (Address: 05h, Bit 0 of R5 = "0")
Bit 7 IOC57 Bit 6 IOC56 Bit 5 IOC55 Bit 4 IOC54 Bit 3 P8HS Bit 2 P8LS Bit 1 P7HS Bit 0 P7LS
Bit 7~4(IOC57~54): PORT 5 I/O direction control register IOC5x = "0": set the relative P5.x I/O pins as output IOC5x = "1": set the relative P5.x I/O pin into high impedance (input pin) Bit 3(P8HS): Switch to high nibble I/O of PORT 8 or to LCD segment output as share pins SEGxx/P8.x pins P8HS = "0": select high nibble of PORT 8 as normal P8.4~P8.7 P8HS = "1": select LCD SEGMENT output as SEG 28~SEG 31 output Bit 2(P8LS): Switch to low nibble I/O of PORT 8 or to LCD segment output as share pins SEGxx/P8.x pins P8LS = "0": select low nibble of PORT 8 as normal P8.0~P8.3 P8LS = "1": select LCD SEGMENT output as SEG 24~SEG 27 output Bit 1(P7HS): Switch to high nibble I/O of PORT 7 or to LCD segment output as share pins SEGxx/P7.x pins P7HS = "0": select high nibble of PORT 7 as normal P7.4~P7.7 P7HS = "1": select LCD SEGMENT output as SEG 20~SEG 23 output Bit 0(P7LS): Switch to low nibble I/O of PORT 7 or to LCD segment output as share pins SEGxx/P7.x pins P7LS = "0": select low nibble of PORT 7 as normal P7.0~P7.3 P7LS = "1": select LCD SEGMENT output as SEG 16~SEG 19 output
4.2.3
IOC60/P6CR (PORT 6 I/O Control Register) (Address: 06h, Bit 0 of R5 = "0")
Bit 7 Bit 6 IOC66 Bit 5 IOC65 Bit 4 IOC64 Bit 3 IOC63 Bit 2 IOC62 Bit 1 IOC61 Bit 0 IOC60
* 19
IOC67
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller Bit 7 (IOC67)~Bit 0(IOC60): PORT 6 I/O direction control register IOC6x ="0": set the relative PORT6.x I/O pins as output IOC6x ="1": set the relative PORT6.x I/O pin into high impedance (input pin)
4.2.4
IOC70/P7CR (PORT 7 I/O Control Register) (Address: 07h, Bit 0 of R5 = "0")
Bit 7 Bit 6 IOC76 Bit 5 IOC75 Bit 4 IOC74 Bit 3 IOC73 Bit 2 IOC72 Bit 1 IOC71 Bit 0 IOC70
IOC77
Bit 7 (IOC77)~Bit 0(IOC70): PORT 7 I/O direction control register IOC7x = "0": set the relative PORT7.x I/O pins as output IOC7x = "1": set the relative PORT7.x I/O pin into high impedance (input pin)
4.2.5
IOC80/P8CR (PORT 8 I/O Control Register) (Address: 08h, Bit 0 of R5 = "0")
Bit 7 Bit 6 IOC86 Bit 5 IOC85 Bit 4 IOC84 Bit 3 IOC83 Bit 2 IOC82 Bit 1 IOC81 Bit 0 IOC80
IOC87
Bit 7 (IOC 87)~Bit 0(IOC 80): PORT 8 I/O direction control register IOC8x = "0": set the relative PORT8.x I/O pins as output IOC8x = "1": set the relative PORT8.x I/O pin into high impedance (input pin)
4.2.6
IOC90/RAM_ADDR (128 Bytes General Purpose RAM Address) (Address: 09h, Bit 0 of R5 = "0")
Bit 7 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0
Bit 7: Not used, fixed at "0" Bit 6~0: 128 bytes RAM address
4.2.7
IOCA0/RAM_DB (128 Bytes General Purpose RAM Data Buffer) (Address: 0Ah, Bit 0 of R5 = "0")
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0 Bit 7~0: 128 bytes RAM data transfer register
4.2.8
IOCB0/CNT1PR (Counter 1 Preset Register) (Address: 0Bh, Bit 0 of R5 = "0")
Bit 7 Bit 7 Bit 6 Bit 6 Bit 5 Bit 5 Bit 4 Bit 4 Bit 3 Bit 3 Bit 2 Bit 2 Bit 1 Bit 1 Bit 0 Bit 0
Bit 7 ~ Bit 0: All are Counter 1 buffer that user can read and write. The Counter 1 is an 8-bit down-count timer/counter with 8-bit pre-scaler that is used as this register to preset
20 * Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller the counter and read preset value. The pre-scaler is set by IOC91 register. After an interruption, it will auto reload the preset value.
4.2.9
IOCC0/CNT2PR (Counter 2 Preset Register) (Address: 0Ch, Bit 0 of R5 = "0")
Bit 7 Bit 7 Bit 6 Bit 6 Bit 5 Bit 5 Bit 4 Bit 4 Bit 3 Bit 3 Bit 2 Bit 2 Bit 1 Bit 1 Bit 0 Bit 0
Bit 7 ~ Bit 0: All are Counter 2 buffer that user can read and write. The Counter 2 is an 8-bit down-count timer with 8-bit pre-scaler that is used as this register to preset the counter and read preset value. The pre-scaler is set by IOC91 register. After an interruption, it will reload the preset value. When IR output is enabled, this control register can obtain carrier frequency output. If the Counter 2 clock source is equal to FT - Carrier frequency (Fcarrier) =
FT 2 * (preset _ value + 1) * prescaler
4.2.10 IOCD0/HPWTPR (High-Pulse Width Timer Preset Register) (Address: 0Dh, Bit 0 of R5 = "0")
Bit 7 Bit 7 Bit 6 Bit 6 Bit 5 Bit 5 Bit 4 Bit 4 Bit 3 Bit 3 Bit 2 Bit 2 Bit 1 Bit 1 Bit 0 Bit 0
Bit 7 ~ Bit 0: All are high-pulse width timer buffer that user can read and write. High-pulse width timer preset register is an eight-bit down-count timer with 8-bit pre-scaler that is used as IOCD0 to preset the counter and read preset value. The pre-scaler is set by IOCA1 register. After an interruption, it will reload the preset value. For PWM or IR application, this control register is set as high pulse width. If the high-pulse width timer source clock is FT - High pulse time =
prescaler * (preset _ value + 1) FT
4.2.11 IOCE0/LPWTPR (Low-Pulse Width Timer Preset Register) (Address: 0Eh, Bit 0 of R5 = "0")
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
Bit 7 ~ Bit 0: All are low-pulse width timer buffer that user can read and write. Low-pulse width timer preset is an eight-bit down-count timer with 8-bit pre-scaler that is used as
IOCE0 to preset the counter and read preset value. The pre-scaler is set by IOCA1 register. After an interruption, it will reload the preset value. For PWM or IR application, this control register is set as low pulse width. If the low-pulse width timer source clock is FT -
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 21
EM78468
8-BIT Microcontroller
prescaler * (preset _ value + 1) FT
Low pulse time =
4.2.12 IOCF0/IMR (Interrupt Mask Register) (Address: 0Fh, Bit 0 of R5 = "0")
Bit 7
ICIE
Bit 6
LPWTE
Bit 5
HPWTE
Bit 4
CNT2E
Bit 3
CNT1E
Bit 2
INT1E
Bit 1
INT0E
Bit 0
TCIE
Bit 7~Bit 0: interrupt enable bit. Enable interrupt source respectively. 0: disable interrupt 1: enable interrupt
IOCF0 register is readable and writable.
Registers of IOC Page 1 (IOC61 ~ IOCE1, Bit 0 of R5 = "1") 4.2.13 IOC61/WUCR (Wake Up and sink current of P5.7/IROUT Control Register) (Address: 06h, Bit 0 of R5 = "1")
Bit 7
IROCS
Bit 6
--
Bit 5
--
Bit 4
--
Bit 3
/WUE8H
Bit 2
/WUE8L
Bit 1
/WUE6H
Bit 0
/WUE6L
Bit 7: IROCS: IROUT/PORT5.7 output sink current set
IROCS
P5.7/IROUT Sink current VDD=5V
9 mA 18 mA
VDD=3V
6 mA 12 mA
0 1
Bit 6,5,4: Not used Bit 3 (/WUE8H): 0/1=> enable/disable P8.4~P8.7 pin change wake up function Bit 2 (/WUE8L): 0/1=> enable/disable P8.0~P8.3 pin change wake up function Bit 1 (/WUE6H): 0/1=> enable/disable P6.4~P6.7 pin change wake up function Bit 0 (/WUE6L): 0/1=> enable/disable P6.0~P6.3 pin change wake up function Port 6 and Port 8 must avoid input floating when wakeup function is enabled. The initial state of wakeup function is enabled.
4.2.14 IOC71/TCCCR (TCC Control Register) (Address: 07h, Bit 0 of R5 = "1")
Bit 7
INT_EDGE
Bit 6
INT
Bit 5
TS
Bit 4
TE
Bit 3
PSRE
Bit 2
TCCP2
Bit 1
TCCP1
Bit 0
TCCP0
Bit 7 (INT_EDGE): INT_EDGE = "0": Interrupt on rising edge of P5.4/INT0 pin
22 * Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller INT_EDGE = "1": Interrupt on falling edge of P5.4/INT0 pin Bit 6 (INT): INT enable flag, this bit is read only INT = "0": interrupt masked by DISI or hardware interrupt INT = "1": interrupt enabled by ENI/RETI instructions Bit 5 (TS): TCC signal source TS = "0": internal instruction cycle clock TS = "1": transition on TCC pin, TCC period > internal instruction clock period Bit 4 (TE): TCC signal edge TE = "0": increment by TCC pin rising edge TE = "1": increment by TCC pin falling edge Bit 3~0 (PSRE, TCCP2~TCCP0): TCC pre-scaler bits. PSRE TCCP2 TCCP1
0 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1
TCCP0
X 0 1 0 1 0 1 0 1
TCC Rate
1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
4.2.15 IOC81/WDTCR (WDT Control Register) (Address: 08h, Bit 0 of R5 = "1")
Bit 7
--
Bit 6
--
Bit 5
--
Bit 4
--
Bit 3
WDTE
Bit 2
WDTP2
Bit 1
WDTP1
Bit 0
WDTP0
Bit 7 ~ 4:Not used Bit 3 (WDTE): watchdog timer enable. This control bit is used to enable the Watchdog
timer,
WDTE = "0": Disable WDT function. WDTE = "1": enable WDT function.
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 23
EM78468
8-BIT Microcontroller Bit 2 ~ 0 (WDTP2 ~ WDTP0): watchdog timer pre-scaler bits. The WDT source clock is sub-oscillation frequency. WDTP2 WDTP1 WDTP0 WDT rate
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
4.2.16 IOC91/CNT12CR (Counter 1, 2 Control Register) (Address: 09h, Bit 0 of R5 = "1")
Bit 7
CNT2S
Bit 6
CNT2P2
Bit 5
CNT2P1
Bit 4
CNT2P0
Bit 3
CNT1S
Bit 2
Bit 1
Bit 0
CNT1P0
CNT1P2 CNT1P1
Bit 7(CNT2S):Counter 2 clock source select 0/1 => Fs/ Fm*
(*Fs: sub-oscillator clock, Fm: main-oscillator clock)
Bit 6~4(CNT2P2~CNT2P0): Counter 2 pre-scaler select bits CNT2P2 CNT2P1 CNT1P0 Counter 2 scale
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 3(CNT1S):Counter 1 clock source select 0/1 => Fs/ Fm Bit 2~0 (CNT1P2~CNT1P0): Counter 1 pre-scaler select bits CNT1P2 CNT1P1 CNT1P0 Counter 1 scale
0 0 0 0 1 1 1 1
24 *
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
4.2.17 IOCA1/HLPWTCR (High/Low Pulse Width Timer Control Register) (Address: 0Ah, Bit 0 of R5 = "1")
Bit 7
LPWTS
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LPWTP2 LPWTP1 LPWTP0
HPWTS HPWTP2 HPWTP1 HPWTP0
Bit 7(LPWTS): low-pulse width timer clock source select 0/1 -> Fs/ Fm*
(*Fs: sub-oscillator clock, Fm: main-oscillator clock)
Bit 6~4 (LPWTP2~ LPWTP0): low-pulse width timer pre-scaler select bits LPWTP2 LPWTP1 LPWTP0 Low-pulse width timer scale
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 3(HPWTS): high-pulse width timer clock source select 0/1 -> Fs/ Fm Bit 2~0(HPWTP2~ HPWTP0): high-pulse width timer pre-scaler select bits HPWTP2 HPWTP1 HPWTP0 High-pulse width timer scale
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
4.2.18 IOCB1/P6PH (PORT 6 Pull High Control Register) (Address: 0Bh, Bit 0 of R5 = "1")
Bit 7
PH67
Bit 6
PH66
Bit 5
PH65
Bit 4
PH64
Bit 3
PH63
Bit 2
PH62
Bit 1
PH61
Bit 0
PH60
Bit 7 ~ Bit 0 (PH67 ~ PH60): The enable bits of PORT 6 pull high function. PH6x = "0": disable pin of P6.x internal pull-high resistor function PH6x = "1": enable pin of P6.x internal pull-high resistor function
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 25
EM78468
8-BIT Microcontroller
4.2.19 IOCC1/P6OD (PORT 6 Open Drain Control Register) (Address: 0Ch, Bit 0 of R5 = "1")
Bit 7
OP67
Bit 6
OP66
Bit 5
OP65
Bit 4
OP64
Bit 3
OP63
Bit 2
OP62
Bit 1
OP61
Bit 0
OP60
Bit 7 ~ Bit 0: The enable bits of PORT 6 open drain function. OD6x = "0": disable pin of P6.x open drain function OD6x = "1": enable pin of P6.x open drain function
4.2.20 IOCD1/P8PH (PORT 8 Pull High Control Register) (Address: 0Dh, Bit 0 of R5 = "1")
Bit 7
PH87
Bit 6
PH86
Bit 5
PH85
Bit 4
PH84
Bit 3
PH83
Bit 2
PH82
Bit 1
PH81
Bit 0
PH80
Bit 7 ~ Bit 0: The enable bits of PORT 8 pull-high function. PH8x = "0": disable pin of P8.x internal pull-high resistor function PH8x = "1": enable pin of P8.x pull-high resistor function
4.2.21 IOCE1/P6PL (PORT 6 Pull-Low Control Register) (Address: 0Eh, Bit 0 of R5 = "1")
Bit 7
PL67
Bit 6
PL66
Bit 5
PL65
Bit 4
PL64
Bit 3
PL63
Bit 2
PL62
Bit 1
PL61
Bit 0
PL60
Bit 7 ~ Bit 0: The enable bits of PORT 6 pull low function. PL6x = "0": disable pin of P6.x internal pull-low resistor function PL6x = "1": enable pin of P6.x internal pull-low resistor function
26 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
4.3
TCC and WDT Pre-scaler
Two 8-bit counters are available as pre-scalers for the TCC (Time Clock Counter) and WDT (Watch Dog Timer). The TCCP2~TCCP0 bits of the IOC71 register are used to determine the ratio of the TCC pre-scaler. Likewise, the WDTP2~WDTP0 bits of the IOC81 register are used to determine the WDT pre-scaler. The TCC pre-scaler (TCCP2~TCCP0) is cleared by the instructions each time they are written into TCC, while the WDT pre-scaler is cleared by the "WDTC" and "SLEP" instructions. Fig.7 depicts the circuit diagram of TCC and WDT. R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be selected by internal instruction clock or external signal input (edge selectable from the TCC control register). If TCC signal source is from internal instruction clock, TCC will increase by 1 at every instruction cycle (without pre-scaler). If TCC signal source is from external clock input, TCC will increase by 1 at every falling edge or rising edge of the TCC pin. The watchdog timer is a free running sub-oscillator. The WDT will keep on running even after the oscillator driver has been turned off. During Normal mode, Green mode, or Idle mode operation, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled at any time during the Normal mode and Green mode by software programming. Refer to WDTE bit of IOC81 register. The WDT time-out period is equal to (pre-scaler*256/ (Fs/2)).
Data Bus
Instruction Clock = Fosc /2 Fosc: CPU operate frequency TCC Pin
TCC (R1)
MUX
Prescaler
8 to 1 MUX
TE (IOC71) TS (IOC71)
PSRE TCCP2~0 (IOC71) (IOC71)
TCCoverflow interrupt
Fig. 7(a) Block Diagram of TCC
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 27
EM78468
8-BIT Microcontroller
WDT
8 bit counter
WDTE (IOC81)
8 to 1 MUX
Prescaler
Fs/2 (Fs:Sub oscillator)
WDT Time out
WDTP2~0 (IOC81)
Fig. 7(b) Block Diagram of WDT
28 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller WDT setting flowchart
START
N
Use WDT function ?
Y
Enable WDT function : set bit 7 of Code option Word 0 to "0" Disable WDT function : set bit 7 of Code option Word 0 to "1"
Setting WDT prescaler (IOC81 register)
WDTtime= prescaler*256/Fs Fs: sub-oscillator frequency
Enable WDT (bit 3 of IOC81)
END
TCC setting flowchart
START
from External Input
TCC clock source? External/ instruction cycle
from Instruction Cycle
*set clock source from external TCC pin (set bit 4 of IOC71 to "1") *set P5.6/TCC for TCC input Pin ( set bit 2 of RE to "1" and set bit 6 of IOC 50 to "1") *choose TCC pin operation edge (set by bit 4 of IOC71) *choose TCC prescaler (set by bit 0 to bit 3 of IOC71)
*choose TCC clock source from instruction cycle (set bit 4 of IOC71 to "0") *choose TCC prescaler (set by bit 0 to bit 3 of IOC71)
* Enable TCC interrupt Mask (set bit 0 of IOCF0 to "1") *Clear TCC interrupt Flag (set bit 0 of RF to "0")
Enable TCC to start count (use ENI instruction)
END
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 29
EM78468
8-BIT Microcontroller
4.4 I/O Ports
The I/O registers, (PORT 5, PORT 6, PORT 7and PORT 8), are bi-directional tri-state I/O ports. PORT 6 and PORT 8 are pulled-high internally by software; PORT 6 is also pulled-low internally by software. Furthermore, PORT 6 has its open-drain output also through software. PORT 6 and PORT 8 features an input status changed interrupt (or wake-up) function and is pulled-high by software. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC50 ~ IOC80). The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits are shown in Fig. 8
NOTE: Open-drain, pull high, and pull down are not shown in the figure.
Fig. 8 The Circuit of I/O Port and I/O Control Register for PORT 5 ~ 8
30 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
4.5
RESET and Wake-up
A reset can be activated by POR (Power On Reset) WDT timeout. (if enabled) /RESET pin go to low.
Note: The power on reset circuit is always enabled. It will reset CPU at about 1.9V.
Once reset occurs, the following functions are performed The oscillator is running, or will be started. The program counter (R2/PC) is set to all "0". All I/O port pins are configured as input mode (high-impedance state). The TCC/Watchdog timer and pre-scaler are cleared. When power on, the Bit 5, 6 of R3 and the upper 2 bits of R4 are cleared. Bits of the IOC71 register are set to all "1" except for Bit 6 (INT flag). For other registers, see Table 2 below.
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 31
EM78468
8-BIT Microcontroller Table 2 Summary of the Initialized Values for Registers Address Name Reset Type Bit 7 Bit 6 Bit 5
0x05 IOC50 (P5CR)
Bit 4
Bit 3
Bit 2
Bit 1
P7HS 0 0 P IOC61 1 1 P IOC71 1 1 P IOC81 1 1 P
Bit 0
P7LS 0 0 P IOC60 1 1 P IOC70 1 1 P IOC80 1 1 P
0x06
IOC60 (P6CR)
0x07
IOC70 (P7CR)
0x08
IOC80 (P8CR)
0x09
IOC90
(RAM_ADDR)
0x0A
IOCA0 (RAM_DB)
0x0B
IOCB0 (CNT1PR)
0x0C
IOCC0 (CNT2PR)
0x0D
IOCD0 (HPWTPR)
0x0E
IOCE0 (LPWTPR)
0x0F
IOCF0 (IMR)
0x06
IOC61 (WUCR)
0x07
IOC71 (TCCCR)
Bit Name IOC57 IOC56 IOC55 IOC54 P8HS P8LS Power-On 1 1 1 1 0 0 /RESET and WDT 1 1 1 1 0 0 Wake-Up from Pin P P P P P P Change Bit Name IOC67 IOC66 IOC65 IOC64 IOC63 IOC62 Power-On 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 Wake-Up from Pin P P P P P P Change Bit Name IOC77 IOC76 IOC75 IOC74 IOC73 IOC72 Power-On 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 Wake-Up from Pin P P P P P P Change Bit Name IOC87 IOC86 IOC85 IOC84 IOC83 IOC82 Power-On 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 Wake-Up from Pin P P P P P P Change Bit Name X RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 Power-On 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 Wake-Up from Pin P P P P P P Change Bit Name RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 Power-On U U U U U U /RESET and WDT P P P P P P Wake-Up from Pin P P P P P P Change Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Power-On 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 Wake-Up from Pin P P P P P P Change Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Power-On 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 Wake-Up from Pin P P P P P P Change Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Power-On 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 Wake-Up from Pin P P P P P P Change Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Power-On 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 Wake-Up from Pin P P P P P P Change Bit Name ICIE LPWTE HPWTE CNT2E CNT1E INT1E Power-On 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 Wake-Up from Pin P P P P P P Change Bit Name IROCS X X X /WUE8H /WUE8L Power-On 0 U U U 0 0 /RESET and WDT 0 U U U 0 0 Wake-Up from Pin P U U U P P Change INT_EDGE Bit Name INT TS TE PSRE TCCP2 Power-On 1 0 1 1 1 1 /RESET and WDT 1 0 1 1 1 1 Wake-Up from Pin P P P P P P Change
RAM_A1 RAM_A0 0 0 0 0 P P RAM_D1 RAM_D0 U U P P P Bit 1 0 0 P Bit 1 0 0 P Bit 1 0 0 P Bit 1 0 0 P INT0E 0 0 P P Bit 0 0 0 P Bit 0 0 0 P Bit 0 0 0 P Bit 0 0 0 P TCIE 0 0 P
/WUE6H /WUE6L 0 0 0 0 P TCCP1 1 1 P P TCCP0 1 1 P
32 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller Address
0x08
Name
IOC81 (WDTCR)
Reset Type
Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change
Bit 7
X U U U CNT2S 0 0 P LPWTS 0 0 P PH67 0 0 P OP67 0 0 P PH87 0 0 P PL67 0 0 P Bit 7 U P P Bit 7 0 0 P Bit 7 0 0 X U U U Bank1 0 0 P R57 1 1 P
Bit 6
X U U U
Bit 5
X U U U
Bit 4
X U U U
Bit 3
WDTE 0 0 P
Bit 2
Bit 1
Bit 0
WDTP2 WDTP1 WDTP0 1 1 1 1 1 1 P P P
0x09
IOC91
(CNT12CR)
CNT2P2 CNT2P1 CNT2P0 CNT1S CNT1P2 CNT1P1 CNT1P0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P P P P P P P LPWTP2 LPWTP1 LPWTP0 HPWTS HPWTP2 HPWTP1 HPWTP0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P PH66 0 0 P OP66 0 0 P PH86 0 0 P PL66 0 0 P Bit 6 U P P Bit 6 0 0 P Bit 6 0 0 PS1 0 0 P Bank0 0 0 P R56 1 1 P P PH65 0 0 P OP65 0 0 P PH85 0 0 P PL65 0 0 P Bit 5 U P P Bit 5 0 0 P Bit 5 0 0 PS0 0 0 P -U P P R55 1 1 P P PH64 0 0 P OP64 0 0 P PH84 0 0 P PL64 0 0 P Bit 4 U P P Bit 4 0 0 P Bit 4 0 0 T 1 t t -U P P R54 1 1 P P PH63 0 0 P OP63 0 0 P PH83 0 0 P PL63 0 0 P Bit 3 U P P Bit 3 0 0 P Bit 3 0 0 P 1 t t -U P P X U U U P PH62 0 0 P OP62 0 0 P PH82 0 0 P PL62 0 0 P Bit 2 U P P Bit 2 0 0 P Bit 2 0 0 Z U P P -U P P X U U U P PH61 0 0 P OP61 0 0 P PH81 0 0 P PL61 0 0 P Bit 1 U P P Bit 1 0 0 P Bit 1 0 0 DC U P P -U P P X U U U P PH60 0 0 P OP60 0 0 P PH80 0 0 P PL60 0 0 P Bit 0 U P P Bit 0 0 0 P Bit 0 0 0 C U P P -U P P
IOCPAGE
0x0A
IOCA1
(HLPWTCR)
0x0B
IOCB1 (P6PH)
0x0C
IOCC1 (P6OD)
0x0D
IOCD1 (P8PH)
0x0E
IOCE1 (P6PL)
0x00
R0 (IAR)
0x01
R1 (TCC)
0x02
R2 (PC)
Jump to address 0x0018 or continue to execute next instruction
0x03
R3 (SR)
0x04
R4 (RSR)
0x05
R5 (PORT5)
0 0 P
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 33
EM78468
8-BIT Microcontroller Address
0x06
Name
R6 (PORT6)
Reset Type
Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
Bit 7
R67 1 1 P R77 1 1 P R87 1 1 P BS 1 1 P X 0 0 P X U U U X 0 0 P X U U U IRE 0 0 P ICIF 0 0 N Bit 7 U P P
Bit 6
R66 1 1 P R76 1 1 P R86 1 1 P DS1 1 1 P X 0 0 P X U U U X 1 1 P CLK2 0 0 P HF 0 0 P
Bit 5
R65 1 1 P R75 1 1 P R85 1 1 P DS0 0 0 P X 0 0 P X U U U X 0 0 0 CLK1 0 0 P LGP 0 0 P
Bit 4
R64 1 1 P R74 1 1 P R84 1 1 P LCDEN 0 0 P
Bit 3
R63 1 1 P R73 1 1 P R83 1 1 P X U U U
Bit 2
R62 1 1 P R62 1 1 P R82 1 1 P 0 0 P
Bit 1
R61 1 1 P R71 1 1 P R81 1 1 P 0 0 P
Bit 0
R60 1 1 P R70 1 1 P R80 1 1 P LCDF0 0 0 P
0x7
R7 (PORT7)
0x8
R8 (PORT8)
LCDTYPE LCDF1
0x9
R9 (LCDCR)
0xA
RA
(LCD_ADDR)
LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0 0 0 0 0 0 0 0 0 0 0 P X U U U X 0 0 P CLK0 0 0 P X U U U CNT2F 0 0 P Bit 4 U P P P P P P LCD_D 0 U P P 0 0 P CPUS *1 *1 P EINT0 0 0 P TCIF 0 0 P Bit 0 U P P
LCD_D 3 LCD_D 2 LCD_D 1 U P P 0 0 P IDLE 1 1 P IROUTE 0 0 P CNT1F 0 0 P Bit 3 U P P U P P 0 0 P BF1 0 0 P TCCE 0 0 P INT1F 0 0 P Bit 2 U P P U P P 0 0 P BF0 0 0 P EINT1 0 0 P INT0F 0 0 P Bit 1 U P P
Power-On RB (LCD_DB) /RESET and WDT Wake-Up from Pin Change Bit Name Power-On RC 0xC /RESET and WDT (CNTER) Wake-Up from Pin Change Bit Name Power-On RD 0xD /RESET and WDT (SBPCR) Wake-Up from Pin Change Bit Name Power-On RE 0xE /RESET and WDT (IRCR) Wake-Up from Pin Change Bit Name Power-On RF 0xF /RESET and WDT (ISR) Wake-Up from Pin Change Bit Name Power-On 0x10~0x3F R10~R3F /RESET and WDT Wake-Up from Pin Change 0xB
LPWTEN HPWTEN CNT2EN CNT1EN
LPWTF HPWTF 0 0 0 0 P Bit 6 U P P P Bit 5 U P P
X: not used. U: unknown or don't care. P: previous value before reset. -: Not defined t : check R3 register explain. N: Monitors interrupt operation status. Note 1: This bit is equal to code option HLFS bit data
34 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
The controller can be awakened from sleep mode and idle mode. The wake-up signals are listed as follows: Wakeup signal Sleep mode Idle mode Green mode Normal mode TCC time out IOCF0 bit0=1 *1 Wake-up + interrupt + next instruction
X
Interrupt
Interrupt
INT0 pin IOCF0 bit1=1 INT1 pin IOCF0 bit2=1 Counter 1 IOCF0 bit3=1 Counter 2 IOCF0 bit4=1 High-pulse timer IOCF0 bit5=1 Low-pulse timer IOCF0 bit6=1
Port6, Port 8
Wake-up Wake-up + interrupt + interrupt + next instruction + next instruction Wake-up Wake-up + interrupt + interrupt + next instruction + next instruction X Wake-up + interrupt + next instruction Wake-up + interrupt + next instruction Wake-up + interrupt + next instruction Wake-up + interrupt + next instruction Wake-up + next instruction
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
X
Interrupt
Interrupt
X
Interrupt
Interrupt
X
Interrupt
Interrupt
(input status change Wake-up wake-up) + next instruction Bit 7 of IOCF0 = "0"
Port6, Port 8
X
X
Wake-up Wake-up (input status change + interrupt + interrupt wake-up) + next instruction + next instruction Bit 7 of IOCF0 = "1" WDT time out X RESET
X RESET
X RESET
Note 1: Only external TCC pin can Wake-up from idle mode.
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 35
EM78468
8-BIT Microcontroller
4.6 Oscillator
4.6.1 Oscillator Modes
This LSI can operate in the three different oscillator modes from main oscillator (R-OSCI, OSCO), such as RC oscillator with external resistor and Internal capacitor mode (ERIC); crystal oscillator mode; and PLL operation mode (R-OSCI connected 0.01F capacitor to Ground). User can select one of them by programming FMMD1 and FMMD0 in the CODE options register. The sub-oscillator can be operated in crystal mode and ERIC mode. Table 3 below shows how these three modes are defined. Table 3 Oscillator Modes as defined by FSMD, FMMD1, FMMD0. FSMD FMMD1 FMMD0 Main clock 0 0 0 1 1 1 0 0 1 0 0 1 0 1 X 0 1 X RC type (ERIC) Crystal type PLL type RC type (ERIC) Crystal type PLL type
Sub-clock
RC type (ERIC) RC type (ERIC) RC type (ERIC) Crystal type Crystal type Crystal type
Table 4 Summary of maximum operating speeds Conditions VDD Fxt max.(MHz) 2.3 Two clocks 3.0 5.0 4 8 10
4.6.2 Phase Lock Loop (PLL Mode)
When operate on PLL mode, the High frequency determined by sub-oscillator. We can choose RD register to change high oscillator frequency. The relation between high frequency (Fm) and sub-oscillator is shown as below table:
R-OSCI
Xin
XTAL
C1
Xout
Rs
C2
Circuit for PLL mode
36 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller Bit 6~4 (CLK2~0) of RD: main clock selection bits for PLL mode (code option select) CLK2 CLK1 CLK0 Main clock Example Fs=32.768K
0 0 0 0 1 0 0 1 1 X 0 1 0 1 X Fs*130 Fs*65 Fs*65/2 Fs*65/4 Fs*244 4.26 MHz 2.13 MHz 1.065 MHz 532 KHz 8 MHz
4.6.3 Crystal Oscillator/Ceramic Resonators (XTAL)
This LSI can be driven by an external clock signal through the R-OSCI pin as shown in Fig.9 below. In most applications, the R-OSCI pin and the OSCO pin can be connected with a crystal or ceramic resonator to generate oscillation. Fig. 10 depicts such circuit. Table 5 provides the recommended values of C1 and C2. Since each resonator has its own attribute, user should refer to its specification for appropriate values of C1 and C2. RS, a serial resistor, may be necessary for AT strip cut crystal or low frequency mode.
R-OSCI
OSCO
Fig.9 Circuit for External Clock Input
C1 C1
R-OSCI
XTAL
Xin
XTAL
OSCO
Rs
C2
Xout
Rs
C2
Fig. 10 Circuit for Crystal/Resonator
Table 5 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonators
Oscillator source
Oscillator Type
Ceramic Resonators
Frequency
455 kHz 2.0 MHz 4.0MHz 455KHz 1.0MHz 2.0MHz 4.0MHz 32.768kHz
C1 (pF)
100~150 20~40 10~30 20~40 15~30 15 15 25
C2 (pF)
100~150 20~40 10~30 20~150 15~30 15 15 25
* 37
Main oscillator Crystal Oscillator
Sub-oscillator
Crystal Oscillator
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
4.6.4 RC Oscillator Mode with Internal Capacitor
If both precision and cost are taken into consideration, This LSI also offers a special oscillation mode, which is equipped with an internal capacitor and an external resistor connected to VDD. The internal capacitor functions as temperature compensator. In order to obtain more accurate frequency, a precise resistor is recommended.
VDD Rext
R-OSCI or Xin
Fig. 11 Circuit for Internal C Oscillator Mode
Table 6 RC Oscillator Frequencies
Pin
R-OSCI Xin
Rext
51k 100k 300k 2.2M
Average Fosc 5V, 25C Average Fosc 3V, 25C
2.2221 MHz 1.1345 MHz 381.36KHz 32.768KHz 2.1972 MHz 1.1203 MHz 374.77 KHz 32.768KHz
Note: Measured from QFP packages with frequency drift of about 30%. Values are provided for design reference only.
4.7 Power-on Considerations
Any microcontroller (as with this LSI) is not warranted to start operating properly before the power supply stabilizes in steady state. This LSI is equipped with Power On Reset (POR) with detection level range of 1.9V to 2.1V. The circuitry eliminates the extra external reset circuit but it will work well only if the VDD rises quickly enough (50 ms or less). However, under critical applications, extra devices are still required to assist in solving power-on problems.
4.7.1
External Power-on Reset Circuit
This circuit implements an external RC to produce a reset pulse (see Fig.12). The pulse width (time constant) should be kept long enough to allow VDD to reach minimum operation voltage. This circuit is used when the power supply rise time is slow. Because the current leakage from the /RESET pin is about 5A, it is recommended that R should not be great than 40K. In this way, the voltage at Pin /RESET is held below 0.2V. The diode (D) acts as a short circuit at power-down. The capacitor, C, is discharged rapidly and fully. Rin, the current-limited resistor, prevents high current discharge or ESD (electrostatic discharge) from flowing into Pin /RESET.
38 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
Fig. 12 External Power on Reset Circuit
4.7.2 Residue-Voltage Protection
When battery is replaced, device power (VDD) is disconnected but residue-voltage remains. The residue-voltage may trips below minimum VDD, but above zero. This condition may cause poor power on reset. Fig.13 and Fig.14 show how to build a residue-voltage protection circuit
Fig. 13 Circuit 1 for the Residue Voltage Protection
Fig. 14 Circuit 2 for the Residue Voltage Protection
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 39
EM78468
8-BIT Microcontroller
4.8 Interrupt
This LSI has eight interrupt sources as listed below: TCC overflow interrupt. External interrupt P5.4/INTO pin External interrupt P5.5/INT1 pin Counter 1 underflow interrupt Counter 2 underflow interrupt High-pulse width timer underflow interrupt Low-pulse width timer underflow interrupt Port 6, Port 8 input status change wake-up This IC has internal interrupts which are falling edge triggered or as follows: TCC timer overflow interrupt, Four 8-bits down-count timer underflow interrupt If these interrupt sources change signal from high to low, the RF register will generate "1" flag to corresponding register if the IOCF0 register is enabled. RF is the interrupt status register. It records the interrupt request in flag bit. IOCF0 is the interrupt mask register. Global interrupt is enabled by ENI instruction and disabled by DISI instruction. When one of the interrupts (when enabled) is generated, it will cause the next instruction to be fetch from address 0003H~0018H according to interrupt source.
40 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
With this LSI, each individual interrupt source has its own interrupt vector as depicted in Table 3. Before the interrupt subroutine is executed, the contents of ACC and the R3 register are initially saved by hardware. After the interrupt service routine is completed, ACC and R3 are restored. The existing interrupt service routine does not allow other interrupt service routine to be executed. So if other interrupts occur while the existing interrupt service routine is being executed, the hardware will save the later interrupts. Only after the existing interrupt service routine is completed that the next interrupt service routine is executed.
InterruptSource ENI/ DISI InterruptOccur
ACC R3
STACKACC STACKR3
RETI
Fig. 15. Interrupt Backup Diagram
Table 3 Interrupt Vector
Interrupt Vector
0003H 0006H 0009H 000CH 000FH 0012H 0015H 0018H
Interrupt Status
TCC overflow interrupt. External interrupt P5.4/INT0 pin External interrupt P5.5/INT1 pin Counter 1 underflow interrupt Counter 2 underflow interrupt High-pulse width timer underflow interrupt Low-pulse width timer underflow interrupt PORT 6, PORT 8 input status change wake-up
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 41
EM78468
8-BIT Microcontroller
4.9 LCD Driver
This LSI can drive LCD of up to 32 segments and 4 commons that can drive 4*32 dots totally. LCD block is made up of LCD driver, display RAM, segment output pins, common output pins, and LCD operating power supply pins. This circuit works on normal mode, green mode and idle mode. The LCD duty; bias; the number of segment; the number of common and frame frequency are determined by the LCD controller register. The basic structure contains a timing control that uses a subsystem clock to generate the proper timing for different duty and display accesses. The R9 register is a command register for LCD driver which includes LCD enable/disable, bias (1/2 and 1/3), duty (1/2, 1/3, 1/4), and LCD frame frequency control. The register RA is an LCD contrast and LCD RAM address control register. The register RB is an LCD RAM data buffer. LCD booster circuit can change operation frequency to improve VLCD2 and VLCD3 drive capability. The control register is explained as follows.
R9/LCDCR (LCD Control Register)
Bit 7
BS
Bit 6
DS1
Bit 5
DS0
Bit 4
LCDEN
Bit 3
--
Bit 2
LCDTYPE
Bit 1
LCDF1
Bit 0
LCDF0
Bit 7 (BS): LCD bias select bit, 0/1=>(1/2 bias) / (1/3 bias) Bit 6 ~ 5 (DS1 ~ DS0): LCD duty select DS1 DS0 LCD Duty
0 0 1 0 1 X 1/2 duty 1/3 duty 1/4 duty
Bit 4 (LCDEN): LCD enable bit: 0/1 -> LCD circuit disable/enable
When LCD function is disabled, all common/segment output is set to ground (GND) level
Bit 3: Not used Bit 2 (LCDTYPE): LCD drive waveform type select bit LCDTYPE = "0": "A" type waveform LCDTYPE = "1": "B" type waveform Bit 1 ~ 0(LCDF1 ~ LCDF0): LCD frame frequency control bits LCD frame frequency (e.g. Fs=32.768KHz) LCDF1 LCDF0 1/2 duty 1/3 duty 1/4 duty
0 0 1 1 0 1 0 1 Fs/(256*2)=64.0 Fs/(280*2)=58.5 Fs/(304*2)=53.9 Fs/(232*2)=70.6 Fs/(172*3)=63.5 Fs/(188*3)=58.0 Fs/(204*3)=53.5 Fs/(156*3)=70.0 Fs/(128*4) =64.0 Fs/(140*4) =58.5 Fs/(152*4) =53.9 Fs/(116*4) =70.6
Fs: sub-oscillator frequency
42 * Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
RA/LCD_ADDR (LCD Address)
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
LCD_A4
Bit 3
LCD_A3
Bit 2
LCD_A2
Bit 1
LCD_A1
Bit 0
LCD_A0
Bit 7 ~ 5: Not used, fixed to "0" Bit 4 ~ 0 (LCDA4 ~ LCDA0): LCD RAM address RA (LCD address) Bit 7 ~4 00H 01H 02H | 1DH 1EH 1FH Common
------|
RB (LCD data buffer)
Bit 3 Bit 2 Bit 1 Bit 0 (LCD_D3) (LCD_D2) (LCD_D1) (LCD_D0)
Segment
SEG0 SEG1 SEG2
|
SEG29 SEG30 SEG31 COM3 COM2 COM1 COM0
X
RB/LCD_DB (LCD Data Buffer)
Bit 7
--
Bit 6
--
Bit 5
--
Bit 4
--
Bit 3
Bit 2
Bit 1
Bit 0
LCD_D 3 LCD_D 2 LCD_D 1 LCD_D 0
Bit 7 ~ 4: Not used Bit 3 ~ 0 (LCD_D3 ~ LCD_D0): LCD RAM data transfer registers
RD/SBPCR (System, Booster and PLL Control Registers)
Bit 7
--
Bit 6
CLK2
Bit 5
CLK1
Bit 4
CLK0
Bit 3
IDLE
Bit 2
BF1
Bit 1
BF0
Bit 0
CPUS
Bit 2 ~ 1 (BF1 ~ 0): LCD booster frequency select bits BF1 BF0 Booster frequency
0 0 1 1 0 1 0 1 Fs Fs/4 Fs/8 Fs/16
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 43
EM78468
8-BIT Microcontroller
IC RESET occur
*Set Port 7 snd Port 8 for general I/O or LCD segment (IOC50) *it must be set to output port w hen the pin of port 7 and the pin of port 8 for LCD segemnt (IOC70 and IOC80)
Set LCD Type, duty, bias, LCD frame frequency (R9)
Set LCD Booster Frequency (RD)
Clear all LCD RAM (RA and RB)
Enable LCD function (R9)
Use LCD address and LCD data buffer to implment user's applications. (RA and RB)
END
Fig.16. The Initial Setting Flowchart for LCD Function
44 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
The connecting of boosting circuits for LCD voltage is as below:
VDD VLCD2(2*VDD/3) VA VLCD3(1*VDD/3) GND
VB
External circuit for 1/3 Bias
VDD VLCD2(VDD/2) VA VLCD3(VDD/2) GND
VB
External circuit for 1/2 Bias
Fig. 17 The Connection of Charge Bump Circuit (Cext=0.1uf )
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 45
EM78468
8-BIT Microcontroller
1 frame VDD COM 0 VLCD2,3 GND VDD COM 1 VLCD2,3 GND VDD SEG N VLCD2,3 GND VDD VLCD2,3 SEG N - COM0 ON GND -VLCD2,3 -VDD VDD VLCD2,3 SEG N - COM1 OFF GND -VLCD2,3 SEG N - COM1 OFF SEG N - COM0 ON SEG N COM 1 COM 0
1 frame VDD VLCD2,3 GND VDD VLCD2,3 GND VDD VLCD2,3 GND VDD VLCD2,3 GND -VLCD2,3 -VDD VDD VLCD2,3 GND -VLCD2,3
1/2 bias, 1/2 duty A type
-VDD
1/2 bias, 1/2 duty B type
-VDD
Fig. 18 LCD Waveform for 1/2 Bias, 1/2 Duty
1frame VDD COM 0 VLCD2,3 GND VDD COM 1 VLCD2,3 GND VDD COM 2 VLCD2,3 GND VDD SEG N VLCD2,3 GND VDD VLCD2,3 SEG N - COM0 ON GND -VLCD2,3 -VDD VDD VLCD2,3 SEG N - COM1 OFF GND -VLCD2,3
SEG N - COM1 OFF SEG N - COM0 ON SEG N COM 2 COM 1 COM 0 1frame VDD VLCD2,3 GND VDD VLCD2,3 GND VDD VLCD2,3 GND VDD VLCD2,3 GND VDD VLCD2,3 GND -VLCD2,3 -VDD VDD VLCD2,3 GND -VLCD2,3
1/2 bias, 1/3 duty A type
-VDD
1/2 bias, 1/3 duty B type
-VDD
Fig. 19 LCD Waveform for 1/2 Bias, 1/3 Duty
46 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
1 frame VDD VLCD2 COM 0 VLCD3 GND VDD VLCD2 COM 1 VLCD3 GND VDD COM 2 VLCD2 VLCD3 GND VDD VLCD2 SEG N VLCD3 GND VDD SEG N - COM0 ON -VLCD3 -VDD VDD SEG N - COM1 OFF -VLCD3 -VDD VLCD3 GND
SEG N - COM1 OFF -VLCD3 -VDD SEG N VLCD3 GND VDD SEG N - COM0 ON -VLCD3 -VDD VDD VLCD3 GND VLCD3 GND COM 2 COM 1 VLCD3 GND VDD VLCD2 VLCD3 GND VDD VLCD2 COM 0 VLCD3 GND VDD VLCD2
1 frame VDD VLCD2
VLCD3 GND
1/3 bias, 1/3 duty A type
1/3 bias, 1/3 duty B type
Fig. 20 LCD Waveform for 1/3 Bias, 1/3 Duty
1frame VDD VLCD2 COM 0 VLCD3 GND VDD VLCD2 COM 1 VLCD3 GND VDD COM 2 VLCD2 VLCD3 GND VDD VLCD2 SEG N VLCD3 GND VDD SEG N COM0 ON -VLCD3 -VDD VDD SEG N COM1 OFF -VLCD3 -VDD VLCD3 GND OFF SEG N COM1 VLCD3 GND ON SEG N COM0 SEG N COM 2 COM 1 COM 0
1frame VDD VLCD2 VLCD3 GND VDD VLCD2 VLCD3 GND VDD VLCD2 VLCD3 GND VDD VLCD2 VLCD3 GND VDD VLCD3 GND -VLCD3 -VDD VDD VLCD3 GND -VLCD3
1/3 bias, 1/4 duty A type
1/3 bias, 1/4 duty B type
-VDD
Fig. 21 LCD Waveform for 1/3 Bias, 1/4 Duty
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 47
EM78468
8-BIT Microcontroller
4.10 Infrared Remote Control Application / PWM Waveform Generate
This LSI can output infrared carrier in a friendly manner or in PWM standard waveform. The IR and PWM waveform generated functions include an 8-bits down-count timer, high-pulse width timer, low-pulse width timer, and IR control register. The IR system block diagram is show in Fig.21, The IROUT pin waveform is determined by IR control register (RE), IOC90 (Counter 1, 2 control register), IOCA0 (high-pulse width timer, low-pulse width timer control register), IOCC0 (Counter 2 preset), IOCD0 (high-pulse width timer preset register), and IOCE0 (low-pulse width timer preset register). Details on Fcarrier, high-pulse time, and low pulse time are explained as follows: If Counter 2 source clock is FT (this clock source can set by IOC91);
Fcarrier = FT 2 * (1 + decimal of counter 2 preset value(IOCC0)) * prescaler
If high-pulse width timer source clock is FT (this clock source can set by IOCA1);
Thigh = prescaler * (1 + decimal of high pulse width timer value(IOCD0)) FT
pulse time
If low-pulse width timer source clock is FT (this clock source can set by IOCA1);
Tlow = prescaler * (1 + decimal of low pulse width timer value(IOCE0)) FT
pulse time
48 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
Pre-s caler (IOCA 1)
Fs
Fm
High-Puls e Width Timer (IOCD0) 8 A uto-reload buf f er Pre-sc aler (IOC A 1)
Low -Pulse Width Timer ( IOCE0) 8 A uto-reload buf f er
8 8 bit dow n counter
8 8 bit dow n counter 8
Pre-scaler (IOC91)
Fcarrier
8 bit dow n counter 8 A uto-reload buf f er 8 Counter 2 (IOCC0) HF LGP
8
H/W Modulator Circuit
IROUTpin
IRE
RE register
Fm: main oscillator frequency; Fs: sub-oscillator frequency Fig. 21 IR/PWM System Block Diagram
The IROUT output waveform is further explained in the following figures:
Fig. 22: LGP=0, HF=1, the IROUT waveform can modulate Fcarrier waveform when in
low-pulse width time.
Fig. 23: LGP=0, HF=0, the IROUT waveform cannot modulate Fcarrier waveform when in low-pulse width time. So IROUT waveform is determined by high-pulse time and low-pulse time. This mode can produce standard PWM waveform Fig. 24: LGP=0, HF=1, the IROUT waveform can modulate Fcarrier waveform when in low-pulse width time. When IRE goes from high to low, the output waveform of IROUT will keep on transmitting till high-pulse width timer interrupt occurs. Fig. 25: LGP=0, HF=0, the IROUT waveform can not modulate Fcarrier waveform when
in low-pulse width time. So IROUT waveform is determined by high-pulse time and low-pulse time. This mode can produce standard PWM waveform. When IRE goes from high to low, the output waveform of IROUT will keep on transmitting till high-pulse width timer interrupt occurs.
Fig.26 : LGP=1, when this bit is set to high level, the high-pulse width timer is ignored. So
IROUT waveform output from low-pulse width timer is established.
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 49
EM78468
8-BIT Microcontroller
Fcarrier
low-pulse width
high-pulse width
low-pulse width
high-pulse width
HF
start
IRE IROUT
Fig. 22 LGP=0, IROUT Pin Output Waveform
Fcarrier
low-pulse width
high-pulse width
low-pulse width
high-pulse width
HF
start
IRE IROUT
Fig. 23 LGP=0, IROUT Pin Output Waveform
Fcarrier
low-pulse width
high-pulse width
low-pulse width
high-pulse width
HF
start
IRE IROUT
IR disable
Always high-level
Fig. 24 LGP=0, IROUT Pin Output Waveform
Fcarrier
low-pulse width
high-pulse width
low-pulse width
high-pulse width
HF
start
IRE IROUT
IR disable
Always high-level
Fig. 25 LGP=0, IROUT Pin Output Waveform
50 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
Fcarrier
low-pulse width
Low-pulse width
low-pulse width
high-pulse width
HF
start
IRE IROUT
IR disable
Always high-level
Fig. 26 LGP=1, IROUT Pin Output Waveform
IR/PWM function enable flowchart
STRAT
SET P5.7 to OUTPUT state (IOC 50)
STRAT
SET P5.7 for IR/PWM Function Output Pin (RE)
SET P5.7 to OUTPUT state (IOC 50)
SET P5.7 for IR/PWM Function Output Pin (RE)
SET Counter 2 clock source and prescaler (IOC91)
SET High pulse width timer, Low pulse width timer source clock and prescaler (IOCA1)
SET High pulse width timer, Low pulse width timer source clock and prescaler (IOCA1)
SET Counter 2 (IOC0), High pulse width timer (IOD0), Low pulse width timer (IOCE0)preset value
High pulse width timer (IOD0), Low pulse width timer (IOCE0)preset value
Enable IR (RE) HF="1", and IRE="1"
Enable IR (RE) HF="0", and IRE="1"
Enable HPWT and LPWT Interrupt Set IOCF0 and ENI instruction
Enable HPWT and LPWT Interrupt Set IOCF0 and ENI instruction
Enable counter 2, high pulse width timer and Low pulde width timer (RC)
Enable high pulse width timer and Low pulde width timer (RC)
END
(a) IR application
END
(b) PWM application
Fig. 27 IR/PWM Function Enable Flowchart
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 51
EM78468
8-BIT Microcontroller
4.11 Code Options
The EM78468 has one Code Option word that is not a part of the normal program memory. Code Option Register (Word 0)
Word 0 Bit12~10 Bit9
1
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3 Bit2 Bit1 Bit0
0 0 0
CYES HLFS ENWDTB FSMD FMMD1 FMMD0 HLP
* Bit 12 ~ 10: Not used. These bits are set to "1" all the time. * Bit 9 (CYES): Cycle select for JMP and CALL instructions
CYES = "0": only one instruction cycle (JMP or CALL) can be executed CYES = "1": two instructions cycles (JMP and CALL) can be executed
* Bit 8 (HLFS): main or sub-oscillator select
HLFS = "0": CPU is set to select sub-oscillator when reset occurs. HLFS = "1": CPU is set to select main-oscillator when reset occurs.
* Bit 7(ENWDTB): Watchdog timer enable/disable bit.
ENWDTB = "0": Enable watchdog timer. ENWDTB = "1": Disable watchdog timer.
* Bit 6 (FSMD): sub-oscillator type selection. * Bit 5, 4 (FMMD1, 0): main Oscillator type selection.
FSMD
0 0 0 1 1 1
FMMD1
0 0 1 0 0 1
FMMD0
0 1 X 0 1 X
Main Oscillator Type
RC type XTAL type PLL type RC type XTAL type PLL type
Sub Oscillator Type
RC type RC type RC type XTAL type XTAL type XTAL type
* Bit 3 (HLP): Power consumption selection. If your system usually runs in green mode, it must be set to low power consumption to help support the energy saving issue. We recommend that low power consumption mode is slected.
HLP = "0": Low power consumption mode HLP = "1": High power consumption mode
* Bit 2~0 : These bits are set to "0" all the time.
52 * Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
4.12 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ). In this case, the execution takes two instruction cycles. If for some reasons, the specification of the instruction cycle is not suitable for certain applications, try modifying the instruction as follows: Execute within two instruction cycles the "JMP", "CALL", "RET", "RETL", & "RETI" instructions, or the conditional skip instructions ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") which were tested to be true. Also execute within two instruction cycles the instructions that are written to the program counter. Additionally, the instruction set offers the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operate on I/O register. The symbol "R" represents a register designator that specifies which one of the registers (including operational registers and general purpose registers) is to be utilized by the instruction. "b" represents a bit field designator that selects the value for the bit that is located in the register "R", and affects operation. "k" represents an 8 or 10-bit constant or literal value.
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 53
EM78468
8-BIT Microcontroller
0 0 0 0 0 0 0 0
INSTRUCTION BINARY 0000 0000 0000 0000 0000 0001 0000 0000 0011 0000 0000 0100 0000 0000 rrrr 0000 0001 0000 0000 0001 0001 0000 0001 0010
HEX
0000 0001 0003 0004 000r 0010 0011 0012
MNEMONIC
NOP DAA SLEP WDTC IOW ENI DISI RET RETI IOR MOV CLRA CLR SUB SUB DECA DEC OR OR AND AND XOR XOR ADD ADD MOV MOV COMA COM INCA INC DJZA DJZ RRCA RRC RLCA RLC R R, A R A, R, R R A, R, A, R, A, R, A, R, A, R, R R R R R R R R R R
OPERATION
No Operation Decimal Adjust A 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC, Enable Interrupt IOCR A AR 0A 0R R-A A R-A R R-1 A R-1 R ARA ARR A& RA A& RR A RA A RR A+RA A+RR RA RR /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) ( A(n-1), R(0) ( C, C ( A(7) R(n) ( R(n-1), R(0) ( C, C ( R(7) R(n) ( A(n+1), R(7) ( C, C ( A(0) R(n) ( R(n+1), R(7) ( C, C ( R(0) R(0-3) ( A(4-7), R(4-7) ( A(0-3) R(0-3) ( R(4-7) R+1 ( A, skip if zero R+1 ( R, skip if zero 0 ( R(b) 1 ( R(b)
R
STATUS AFFECTED None C T, P T, P None None None None
None None None Z Z Z, C, DC Z, C, DC Z Z Z Z Z Z Z Z Z, C, DC Z, C, DC Z Z Z Z Z Z None None C C C C None None None None None None
0 0000 0001 0011 0013 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0001 0001 0001 0001 0010 0010 0010 0010 0011 0011 0011 0011 0100 0100 0100 0100 0101 0101 0101 0101 0001 01rr 1000 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr rrrr rrrr 0000 rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr 001r 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx
R A
R A R A R A R A R R
0 0110 00rr 0 0110 01rr 0 0110 10rr 0 0110 11rr 0 0111 0 0 0 0 0
54 *
00rr 01rr 10rr 11rr bbrr bbrr
SWAPA R SWAP JZA JZ BC BS R R R R, b R, b
0111 0111 0111 100b 101b
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller INSTRUCTION BINARY 0 110b bbrr rrrr 0 111b bbrr rrrr
1 00kk 1 1 1 1 1 1 1 1 1 1 01kk 1000 1001 1010 1011 1100 1101 1110 1110 1111 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 1000 1001 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 00kk 00kk kkkk
HEX
0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E8k 1E9K 1Fkk
MNEMONIC
JBC JBS CALL JMP MOV OR AND XOR RETL SUB PAGE BANK ADD R, b R, b k k A, A, A, A, k A, k k A, k k k k k
OPERATION
if R(b)=0, skip if R(b)=1, skip PC+1 [SP], (Page, k) PC (Page, k) PC kA Ak A A&kA A kA k A, [Top of Stack] PC k-A A k->R5(1:0) k->R4(7:6) k+A A
STATUS AFFECTED None None
None None None Z Z Z None Z, C, DC None None Z, C, DC
k
This instruction is applicable to IOC50 ~ IOCF0, IOC61 ~ IOCE1
4.13
Timing Diagram
AC Test Input/Output Waveform
2.4
2.0 0.8
TEST POINTS
2.0 0.8
0.4
AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Tim ing m easurem ents are m ade at 2.0V for logic "1",and 0.8V for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1 Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins CLK
TCC
Ttcc
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 55
EM78468
8-BIT Microcontroller
Ttrf 90% Port (n+1) Tiod 10% Ttrr 90% 10%
Port (n)
*n=0246
5
ABSOLUTE MAXIMUM RATINGS
Items
Supply voltage Input voltage Output voltage Operation temperature Storage temperature Power dissipation Operating Frequency
Symbol
VDD VI VO TOPR TSTG PD
Condition
Rating Min.
GND-0.3
Max.
+7.0
Unit
V V V

PORT 5, PORT 6, PORT 7, PORT 8 GND-0.3 VDD+0.3 PORT 5, PORT 6, PORT 7, PORT 8 GND-0.3 VDD+0.3 0 -65 32.768K 70 150 500 10M
mW Hz
56 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
6
ELECTRICAL CHARACTERISTIC
6.1 DC ELECTRICAL CHARACTERISTICS
(Ta= 25 C, VDD= 5.0V, GND= 0V)
Symbol
FXT Fs
Parameter
XTAL: VDD to 5V Sub-oscillator External R, internal C for sub-oscillator External R, internal C for sub-oscillator
Condition
Two cycle with two clocks Two cycle with two clocks R: 300K, internal capacitance R: 2.2M, internal capacitance
Min.
32.768K
Typ.
8M 32.768
Max.
10M
Unit
Hz KHz
270 22.9 -1 2.4
384 32.768 0
500 42.6 1
KHz KHz
A
ERIC
IIL VIH1 VIL1 VIHT1 VILT1 VIHT2 VILT2 IOH1 IOL1 IOH1 IOL2 IPH IPL ISB ICC1
Input Leakage Current for input VIN = VDD, GND pins I Input High Threshold Voltage Ports 5, 6, 7, 8 (Schmitt trigger) Input High Threshold Voltage (Schmitt trigger) Input High Threshold Voltage (Schmitt trigger) Input Low Threshold Voltage (Schmitt trigger) Input High Threshold Voltage (Schmitt trigger) Input Low Threshold Voltage (Schmitt trigger) Output High Voltage (Ports 5, 6, 7, 8) Output Low Voltage (Ports 5, 6, 7, 8) Output high voltage (P5.7/IROUT pin) Output Low Voltage (P5.7/IR OUT pin) Pull-high current Pull-low current Sleep mode current Idle mode current Ports 5, 6, 7, 8 /RESET /RESET TCC, INT0, INT1 TCC, INT0, INT1 VOH = 2.4V, IROCS="0" VOL = 0.4V, IROCS="0" VOH = 2.4V, IROCS="1" VOL = 0.4V, IROCS="1 Pull-high active, input pin at GND Pull-low active, input pin at VDD All input and I/O pins at VDD, output pin floating, WDT disabled /RESET= 'High', CPU OFF, sub-oscillator clock (32.768KHz) ON, output pin floating, LCD enable, no load /RESET= 'High', CPU ON, used sub-oscillator clock (32.768KHz), output pin floating, WDT enabled, LCD enable /RESET= 'High', Fosc=4MHz (Crystal type, CLKS="0"), output pin floating /RESET= 'High', Fosc=10MHz (Crystal type, CLKS="0"), output pin floating
V 0.8 V V 0.8 V V 0.8 V mA 9 mA mA 18 mA
A A A A
2.4
2.4
-9
-18
-55 55
-75 75 0.5 14
-95 95 1.5 18
ICC2 ICC3 ICC4
Green mode current Normal mode Normal mode
22 2.2 3.1
30 3 4
A
mA mA
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 57
EM78468
8-BIT Microcontroller
(Ta= 25 C, VDD= 3.0V, GND= 0V)
Symbol
FXT Fs ERIC
Parameter
XTAL: VDD to 5V Sub-oscillator External R, internal C for sub-oscillator External R, internal C for sub-oscillator
Condition
Two cycle with two clocks Two cycle with two clocks R: 300K, internal capacitance R: 2.2M, internal capacitance
Min.
32.768K
Typ.
8M 32.768
Max.
10M
Unit
Hz KHz
270 22.9 -1 1.8
384 32.768 0
500 42.6 1
KHz KHz
A
IIL VIH1 VIL1 VIHT1 VILT1 VIHT2 VILT2 IOH1 IOL1 IOH1 IOL2 IPH IPL ISB ICC1
Input Leakage Current for input VIN = VDD, GND pins Input High Threshold Voltage (Schmitt trigger) Input Low Threshold Voltage (Schmitt trigger) Input High Threshold Voltage (Schmitt trigger) Input Low Threshold Voltage (Schmitt trigger) Input High Threshold Voltage (Schmitt trigger) Input Low Threshold Voltage (Schmitt trigger) Output High Voltage (Ports 5, 6, 7, 8) Output Low Voltage (Ports 5, 6, 7, 8) Output high voltage (P5.7/IROUT pin) Output Low Voltage (P5.7/IR OUT pin) Pull-high current Pull-low current Sleep mode current Idle mode current Ports 5, 6, 7, 8 Ports 5, 6, 7, 8 /RESET /RESET TCC, INT0, INT1 TCC, INT0, INT1 VOH = 2.4V, IROCS="0" VOL = 0.4V, IROCS="0" VOH = 2.4V, IROCS="1 VOL = 0.4V, IROCS="1 Pull-high active, input pin at GND Pull-low active, input pin at VDD All input and I/O pins at VDD, output pin floating, WDT disabled /RESET= 'High', CPU OFF, sub-oscillator clock (32.768KHz) ON, output pin floating, LCD enable, no load /RESET= 'High', CPU ON, used sub-oscillator clock (32.768KHz), output pin floating, WDT enabled, LCD enable /RESET= 'High', Fosc=4MHz (Crystal type, CLKS="0"), output pin floating
V 0.6 V V 0.6 V V 0.6 V mA 6 mA mA 12 mA
A A A A
1.8
1.8
-1.8
-3.5
-16 16
-23 23 0.1 4
-30 30 1 8
ICC2 ICC3
Green mode current Normal mode
10 0.73
20 1.2
A
mA
58 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
6.2 AC Electrical Characteristics
(Ta=- 40C ~ 85 C, VDD=5V5%, GND=0V)
Symbol
Dclk Tins Ttcc Tdrh Trst Twdt Tset Thold Tdelay
Parameter
Input CLK duty cycle Instruction cycle time (CLKS="0") TCC input period Device reset hold time /RESET pulse width Watchdog timer period Input pin setup time Input pin hold time Output pin delay time
Conditions
Crystal type RC type Ta = 25C Ta = 25C Ta = 25C
Min
45 100 500 (Tins+20)/N* 11.3 2000 11.3
Typ
50
Max
55 DC DC
Unit
% ns ns ns ms ns ms ns ns ns
16.2 16.2 0 20
21.6 21.6
Cload=20pF
50
* N= selected pre-scaler ratio.
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 59
EM78468
8-BIT Microcontroller
7
APPLICATION CIRCUIT
COM0 | COM3 SEG0 | SEG31 IROUT P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 1 5 9 D 2 6 A E 3 7 B F 4 8 C G LCD PANEL VDD
Fig. 28 IROUT control external BJT circuit to drive infrared emitting diodes
EM78468
COM0 | COM3 SEG0 | SEG31 IROUT P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 1 5 9 D
LCD PANEL VDD
EM78468
2 6 A E
3 7 B F
4 8 C G
Fig. 29 IROUT direct drive infrared emitting diodes
60 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
APPENDIX A
A.1 Package Types
Name
EM78468H EM78468Q EM78468AQ EM78468BQ EM78468CQ
Package Type
Dice QFP LQFO LQFP QFP
Pin Count
59 64 64 44 44
Package Body Size
14 mm * 20 mm 7 mm * 7mm 10 mm * 10 mm 10 mm * 10 mm
A.2 Package Information QFP - 64
Symbal A A1 A2 D D1 E E1 c L L1 b e Normal Max 3.40 2.72 3.05 25.00 BASIC 20.00 BASIC 19.00 BASIC 14.00 BASIC 0 7 3.5 0.11 0.15 0.23 1.15 1.3 1.45 2.50 REF 0.35 0.50 0.4 1.00 BSC Min 0.25 2.55
A1
TITLE: QFP-64 L(14*20 MM) FOOTPRINT 5.0mm PACKAGE OUTLINE DIMENSION
File :
QFP 64L
Edtion: A Unit : mm
Scale: Free
Material: Sheet:1 of 1
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 61
EM78468
8-BIT Microcontroller
LQFP - 64
DETAIL " A " D D1
L
L1
64
Symbal A A1 A2 D D1 E E1 e c c1 b b1 L L1
Min 0.05 1.35 8.90 6.90 8.90 6.900 0.09 0.09 0.13 0.13 0.45 0
1 b
e
Normal 1.40 9.00 7.00 9.00 7.00 0.4 BSC 0.18 0.16 0.60 1.00 REF. 3.5
Max 1.60 0.15 1.45 9.10 7.10 9.10 7.100 0.20 0.16 0.23 0.19 0.75 7
E E1
A2
A
TITLE: A1
LQFP 64L ( 7*7 MM ) FOOTPRINT 2.0 mm PACKAGE OUTLINE DIMENSION
DETAIL " B "
c1
b b1
File :
LQFP 64L
c
Edtion: A Unit : mm
Scale: Free
Material: Sheet:1 of 1
62 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
LQFP - 44
Symbal A A1 A2 b c E1 E L L1 e Min 0.050 1.350 0.300 0.090 Normal Max 1.600 0.150 1.450 0.450 0.200
1.400 0.370
c
12.00 BASIC 10.00 BASIC 0.450 0.600 0.750 1.0(BASIC) 0.8(BASIC) 0 3.5 7
TITLE: LQFP-44L(10*10 MM) FOOTPRINT 2.0mm PACKAGE OUTLINE DIMENSION
File :
LQFP44
Edtion: A Unit : mm
Scale: Free
Material: Sheet:1 of 1
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 63
EM78468
8-BIT Microcontroller
QFP - 44
Symbal A A1 A2 b c E1 E L L1 e Min 0.15 1.80 Normal Max 2.70 0.50 2.20
c
13.00 9.90 0.73 1.50 0
2.00 0.30(TYP) 0.15(TYP) 13.20 10.00 0.88 1.60 0.80(TYP)
13.40 10.10 1.03 1.70 7
TITLE: QFP-44L(10*10 MM) FOOTPRINT 3.2mm PACKAGE OUTLINE DIMENSION
File :
QFP44
Edtion: A Unit : mm
Scale: Free
Material: Sheet:1 of 1
64 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
EM78468
8-BIT Microcontroller
APPENDIX B
B.1 ICE 468XA Oscillator circuit (JP 5)
Mode1:
Main oscillator: Crystal mode, Sub oscillator: Crystal mode
Crystal
GND Xin R-OSCI Xout OSCO GND GND VDD VDD Xin R-OSCI
Suboscillator Mainoscillator
JP 5
GND
Crystal
Mode2:
Main oscillator: PLL mode, Sub oscillator: Crystal mode
Crystal
GND Xin R-OSCI Xout OSCO GND GND VDD VDD Xin R-OSCI
Suboscillator Mainoscillator
JP 5
GND
PLL
Mode3:
Main oscillator: RC mode, Sub oscillator: Crystal
Crystal Suboscillator Mainoscillator
GND
Xin R-OSCI
Xout OSCO
GND GND
VDD VDD
Xin R-OSCI
JP 5
GND
RC
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
* 65
EM78468
8-BIT Microcontroller
Mode4:
Main oscillator: Crystal mode, Sub oscillator: RC mode
RC
GND Xin R-OSCI Xout OSCO GND GND VDD VDD Xin R-OSCI
Suboscillator Mainoscillator
JP 5
GND
Crystal
Mode5:
Main oscillator: PLL mode, Sub oscillator: RC mode
RC Suboscillator Mainoscillator
GND
Xin R-OSCI
Xout OSCO
GND GND
VDD VDD
Xin R-OSCI
JP 5
GND
PLL
Mode6:
Main oscillator: RC mode, Sub oscillator: RC mode
RC
GND Xin R-OSCI Xout OSCO GND GND VDD VDD Xin R-OSCI
Suboscillator Mainoscillator
JP 5
GND
RC
66 *
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
JP 3
VB VA VLCD3 GND OSCO Xin 1 4 3 6 5 7 2 VLCD2 /RESET R-OSCI VDD Xout P5.5/INT1 P5.7/IROUT P6.1 P6.3 P6.5 P6.7 SEG30/P8.6 SEG28/P8.4 SEG26/P8.2 SEG24/P8.0 SEG22/P7.6 SEG20/P7.4 SEG18/P7.2 SEG16/P7.0 SEG14 SEG12 SEG10 SEG8 SEG6 SEG4 SEG2 SEG0 COM2 COM0
P5.4/INT0 P5.6/TCC P6.0 P6.2 P6.4 P6.6 SEG31/P8.7 SEG29/P8.5 SEG27/P8.3 SEG25/P8.1 SEG23/P7.7 SEG21/P7.5 SEG19/P7.3 SEG17/P7.1 SEG15 SEG13 SEG11 SEG9 SEG7 SEG5 SEG3 SEG1 COM3 COM1
Product Specification (V1.1) 04.11.2005
(This specification is subject to change without further notice)
B.2 ICE 468XA output pin assignment (JP 3)
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
EM78468
8-BIT Microcontroller
* 67

▲Up To Search▲

Price & Availability of EM78468Q

	To Download EM78468Q Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .